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| author | Jisheng Zhang | 2016-03-16 12:40:33 +0100 |
|---|---|---|
| committer | Bjorn Helgaas | 2016-04-06 00:04:27 +0200 |
| commit | 7e57fd1444bf8f4ba9179f826ed6817c56b801d4 (patch) | |
| tree | dd7776751a04341f7f6854b31d2374cc3d158d0e /drivers/pci/host/pci-dra7xx.c | |
| parent | Linux 4.6-rc2 (diff) | |
| download | kernel-qcow2-linux-7e57fd1444bf8f4ba9179f826ed6817c56b801d4.tar.gz kernel-qcow2-linux-7e57fd1444bf8f4ba9179f826ed6817c56b801d4.tar.xz kernel-qcow2-linux-7e57fd1444bf8f4ba9179f826ed6817c56b801d4.zip | |
PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc()
programs the Root Complex registers. The Root Complex may lose power
during suspend-to-RAM, and when we resume, we want to redo the latter but
not the former.
Move some Root Complex programming from dw_pcie_host_init() to
dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call
dw_pcie_setup_rc() in their resume paths.
[Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU
programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the
dra7xx pp->mem_base update before calling dw_pcie_setup_rc().]
[bhelgaas: changelog, fold in dra7xx fix from Niklas]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'drivers/pci/host/pci-dra7xx.c')
| -rw-r--r-- | drivers/pci/host/pci-dra7xx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c index 2ca3a1f30ebf..f441130407e7 100644 --- a/drivers/pci/host/pci-dra7xx.c +++ b/drivers/pci/host/pci-dra7xx.c @@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) static void dra7xx_pcie_host_init(struct pcie_port *pp) { - dw_pcie_setup_rc(pp); - pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; + dw_pcie_setup_rc(pp); + dra7xx_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) dw_pcie_msi_init(pp); |