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authorSinan Kaya2018-01-22 21:12:01 +0100
committerBjorn Helgaas2018-02-28 22:00:55 +0100
commit04875177dbe034055f23960981ecf6fb8ea1d638 (patch)
treee16bd69b4a1c3b5962bb5651dfab7c6d052c6ef4 /drivers/pci/pcie/aspm.c
parentPCI/ASPM: Declare threshold_ns as u32, not u64 (diff)
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PCI/ASPM: Don't warn if already in common clock mode
Previously we emitted a warning if we tried to configure common clock mode the link was already configured to common clock mode by the UEFI BIOS. Bail out silently in that case instead of emitting the warning: pci 0004:00:00.0: ASPM: Could not configure common clock Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Diffstat (limited to 'drivers/pci/pcie/aspm.c')
-rw-r--r--drivers/pci/pcie/aspm.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 8633fc4e1c11..95a2f222b64e 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -228,6 +228,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
if (!(reg16 & PCI_EXP_LNKSTA_SLC))
same_clock = 0;
+ /* Port might be already in common clock mode */
+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
+ if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
+ bool consistent = true;
+
+ list_for_each_entry(child, &linkbus->devices, bus_list) {
+ pcie_capability_read_word(child, PCI_EXP_LNKCTL,
+ &reg16);
+ if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
+ consistent = false;
+ break;
+ }
+ }
+ if (consistent)
+ return;
+ pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
+ }
+
/* Configure downstream component, all functions */
list_for_each_entry(child, &linkbus->devices, bus_list) {
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);