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| author | David Woodhouse | 2009-05-10 21:18:18 +0200 |
|---|---|---|
| committer | David Woodhouse | 2009-05-10 21:18:18 +0200 |
| commit | 462b60f6ccc685f7e8aa04ff430e6b4ffedf629f (patch) | |
| tree | 5f034b5c4993311147f78285a4ffab37def99ed6 /drivers/pci | |
| parent | intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing. (diff) | |
| download | kernel-qcow2-linux-462b60f6ccc685f7e8aa04ff430e6b4ffedf629f.tar.gz kernel-qcow2-linux-462b60f6ccc685f7e8aa04ff430e6b4ffedf629f.tar.xz kernel-qcow2-linux-462b60f6ccc685f7e8aa04ff430e6b4ffedf629f.zip | |
intel-iommu: Fix tiny theoretical race in write-buffer flush.
In iommu_flush_write_buffer() we read iommu->gcmd before taking the
register_lock, and then we mask in the WBF bit and write it to the
register.
There is a tiny chance that something else could have _changed_
iommu->gcmd before we take the lock, but after we read it. So we could
be undoing that change.
Never actually going to have happened in practice, since nothing else
changes that register at runtime -- aside from the write-buffer flush
it's only ever touched at startup for enabling translation, etc.
But worth fixing anyway.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/intel-iommu.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index f47d04aced87..2e2c7406131d 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -844,10 +844,8 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu) if (!rwbf_quirk && !cap_rwbf(iommu->cap)) return; - val = iommu->gcmd | DMA_GCMD_WBF; - spin_lock_irqsave(&iommu->register_lock, flag); - writel(val, iommu->reg + DMAR_GCMD_REG); + writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); /* Make sure hardware complete it */ IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |