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| author | Paul Burton | 2017-08-15 23:25:25 +0200 |
|---|---|---|
| committer | Bjorn Helgaas | 2017-08-16 18:44:37 +0200 |
| commit | aac2e96bf9cce2bc61c13709d361875d2dbf098d (patch) | |
| tree | 013681a8f302d5d464b70f43e26f46d1e8c4d9b8 /drivers/pci | |
| parent | PCI: xilinx: Unify INTx & MSI interrupt decode (diff) | |
| download | kernel-qcow2-linux-aac2e96bf9cce2bc61c13709d361875d2dbf098d.tar.gz kernel-qcow2-linux-aac2e96bf9cce2bc61c13709d361875d2dbf098d.tar.xz kernel-qcow2-linux-aac2e96bf9cce2bc61c13709d361875d2dbf098d.zip | |
PCI: xilinx: Don't enable config completion interrupts
The Xilinx AXI bridge for PCI Express device provides interrupts indicating
the completion of config space accesses. We have previously
enabled/unmasked them but do nothing with them besides acknowledge them.
Leave the interrupts masked in order to avoid servicing a large number of
pointless interrupts during boot.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-xilinx.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index a7880bed56fc..f30d03309c7f 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -60,6 +60,7 @@ #define XILINX_PCIE_INTR_MST_SLVERR BIT(27) #define XILINX_PCIE_INTR_MST_ERRP BIT(28) #define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED +#define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D #define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF /* Root Port Error FIFO Read Register definitions */ @@ -554,8 +555,8 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IDR); - /* Enable all interrupts */ - pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR); + /* Enable all interrupts we handle */ + pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR); /* Enable the Bridge enable bit */ pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) | |