diff options
| author | Joao Pinto | 2016-08-10 12:02:38 +0200 |
|---|---|---|
| committer | Bjorn Helgaas | 2016-08-17 21:43:39 +0200 |
| commit | c388de1c4f0e5da3e96b49efb0388e2a0d34e079 (patch) | |
| tree | 1fd8f629dadcbdf3ded9cfe8ddf0511df068c0e2 /drivers/pci | |
| parent | PCI: designware: Return data directly from dw_pcie_readl_rc() (diff) | |
| download | kernel-qcow2-linux-c388de1c4f0e5da3e96b49efb0388e2a0d34e079.tar.gz kernel-qcow2-linux-c388de1c4f0e5da3e96b49efb0388e2a0d34e079.tar.xz kernel-qcow2-linux-c388de1c4f0e5da3e96b49efb0388e2a0d34e079.zip | |
PCI: designware: Move link wait definitions to .c file
Move the link wait sleep definitions to the .c file as suggested by
Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jisheng Zhang <jszhang@marvell.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 5 | ||||
| -rw-r--r-- | drivers/pci/host/pcie-designware.h | 5 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 1f6bd6d42874..e99f56ecd61d 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -26,6 +26,11 @@ #include "pcie-designware.h" +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + /* Synopsis specific PCIE configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_MODE_MASK (0x3f << 16) diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 74a8fc6abdba..285e1edc505b 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -22,11 +22,6 @@ #define MAX_MSI_IRQS 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct pcie_port { struct device *dev; u8 root_bus_nr; |