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authorAndy Shevchenko2019-04-01 14:06:44 +0200
committerAndy Shevchenko2019-05-20 14:04:25 +0200
commite58926e781d81bb4efc90fada08183c3f04478de (patch)
treea12c016f50b4e036c504d1dd336517eff7b0e189 /drivers/pinctrl/intel
parentLinux 5.2-rc1 (diff)
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pinctrl: intel: Use GENMASK() consistently
Use GENMASK() macro for all definitions. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/pinctrl/intel')
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index d7acbb79cdf7..68950508bfd2 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -33,13 +33,13 @@
#define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
-#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
+#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
-#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
+#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
#define PADCFG0_RXEVCFG_LEVEL 0
#define PADCFG0_RXEVCFG_EDGE 1
#define PADCFG0_RXEVCFG_DISABLED 2
@@ -51,7 +51,7 @@
#define PADCFG0_GPIROUTSMI BIT(18)
#define PADCFG0_GPIROUTNMI BIT(17)
#define PADCFG0_PMODE_SHIFT 10
-#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
+#define PADCFG0_PMODE_MASK GENMASK(13, 10)
#define PADCFG0_GPIORXDIS BIT(9)
#define PADCFG0_GPIOTXDIS BIT(8)
#define PADCFG0_GPIORXSTATE BIT(1)
@@ -60,7 +60,7 @@
#define PADCFG1 0x004
#define PADCFG1_TERM_UP BIT(13)
#define PADCFG1_TERM_SHIFT 10
-#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
+#define PADCFG1_TERM_MASK GENMASK(12, 10)
#define PADCFG1_TERM_20K 4
#define PADCFG1_TERM_2K 3
#define PADCFG1_TERM_5K 2