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| author | Thomas Petazzoni | 2015-06-09 18:47:15 +0200 |
|---|---|---|
| committer | Linus Walleij | 2015-06-10 14:00:54 +0200 |
| commit | 50a7d13d241081838c6cd12b1fdabc36838f9b4c (patch) | |
| tree | f4aad06b6655ddc078037c2510619a7ef358542c /drivers/pinctrl/mvebu | |
| parent | pinctrl: mvebu: armada-370: align spi1 clock pin naming (diff) | |
| download | kernel-qcow2-linux-50a7d13d241081838c6cd12b1fdabc36838f9b4c.tar.gz kernel-qcow2-linux-50a7d13d241081838c6cd12b1fdabc36838f9b4c.tar.xz kernel-qcow2-linux-50a7d13d241081838c6cd12b1fdabc36838f9b4c.zip | |
pinctrl: mvebu: armada-xp: rename spi to spi0
After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.
In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.
This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mvebu')
| -rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index fb5ffa57d90d..74ff2118a9ed 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -224,25 +224,25 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)), MPP_MODE(36, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "mosi", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)), MPP_MODE(37, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "miso", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)), MPP_MODE(38, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "sck", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)), MPP_MODE(39, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)), MPP_MODE(40, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x1, "spi", "cs2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), @@ -257,32 +257,32 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs4", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs5", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs6", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x3, "spi", "cs7", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), MPP_MODE(48, |