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| author | Geert Uytterhoeven | 2016-10-03 14:49:57 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven | 2017-03-30 13:43:45 +0200 |
| commit | b205914c8f822ef2464b741c64e892823d685ad6 (patch) | |
| tree | d1dd7c1c1688274ca26dfe5ae184ae9af98b89c1 /drivers/pinctrl/sh-pfc/Makefile | |
| parent | pinctrl: sh-pfc: Update info pointer after SoC-specific init (diff) | |
| download | kernel-qcow2-linux-b205914c8f822ef2464b741c64e892823d685ad6.tar.gz kernel-qcow2-linux-b205914c8f822ef2464b741c64e892823d685ad6.tar.xz kernel-qcow2-linux-b205914c8f822ef2464b741c64e892823d685ad6.zip | |
pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0
The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
Hence this patch:
1. Extracts the support for R-Car H3 ES1.x into a separate file, as
the differences are quite large,
2. Adds code for detecting the SoC revision at runtime using the new
soc_device_match() API, and selecting pinctrl tables for the actual
SoC revision,
3. Replaces the core register and bitfield definitions by their
counterparts for R-Car H3 ES2.0.
The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.
The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/Makefile')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 2dda8c63f3cf..8e08684774af 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o +obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o |