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author | Xing Zheng | 2016-03-09 03:37:03 +0100 |
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committer | Heiko Stuebner | 2016-03-27 13:03:33 +0200 |
commit | 268aebaa2410152bf91ea1ede6b284ff8138822d (patch) | |
tree | f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0 /drivers/ras | |
parent | clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type (diff) | |
download | kernel-qcow2-linux-268aebaa2410152bf91ea1ede6b284ff8138822d.tar.gz kernel-qcow2-linux-268aebaa2410152bf91ea1ede6b284ff8138822d.tar.xz kernel-qcow2-linux-268aebaa2410152bf91ea1ede6b284ff8138822d.zip |
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/ras')
0 files changed, 0 insertions, 0 deletions