diff options
| author | Andrew Vasquez | 2009-06-03 18:55:26 +0200 |
|---|---|---|
| committer | James Bottomley | 2009-06-08 21:46:54 +0200 |
| commit | aed10881129c52f0e5dc1c96ac706b5ce7708a13 (patch) | |
| tree | 7c5e83f9d1f318f581792a0e2988aa44dd5ac7e6 /drivers/scsi | |
| parent | [SCSI] qla2xxx: Avoid redundant RISC reset during (re)-initialization. (diff) | |
| download | kernel-qcow2-linux-aed10881129c52f0e5dc1c96ac706b5ce7708a13.tar.gz kernel-qcow2-linux-aed10881129c52f0e5dc1c96ac706b5ce7708a13.tar.xz kernel-qcow2-linux-aed10881129c52f0e5dc1c96ac706b5ce7708a13.zip | |
[SCSI] qla2xxx: Query supported RISC registers bits in determining a paused-state.
ISP24xx and above must query the host-status register, not HCCR.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
Diffstat (limited to 'drivers/scsi')
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 6 | ||||
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_fw.h | 1 |
2 files changed, 2 insertions, 5 deletions
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 68671a2b8b7f..4a990f4da4ea 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -149,11 +149,9 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) int rval = QLA_SUCCESS; uint32_t cnt; - if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) - return rval; - WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); - for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && + for (cnt = 30000; + ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && rval == QLA_SUCCESS; cnt--) { if (cnt) udelay(100); diff --git a/drivers/scsi/qla2xxx/qla_fw.h b/drivers/scsi/qla2xxx/qla_fw.h index 9e56d4a4cb75..dfde2dd865cb 100644 --- a/drivers/scsi/qla2xxx/qla_fw.h +++ b/drivers/scsi/qla2xxx/qla_fw.h @@ -878,7 +878,6 @@ struct device_reg_24xx { /* HCCR statuses. */ #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ -#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */ /* HCCR commands. */ /* NOOP. */ #define HCCRX_NOOP 0x00000000 |