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| author | Pierre-Louis Bossart | 2019-05-01 17:57:39 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2019-05-02 17:16:28 +0200 |
| commit | 7cc6e315317fe3a077fa474941a3ebf93fc15e78 (patch) | |
| tree | a5de2c101a696d5a9ff976b8cf26db4085ef61d9 /drivers/soundwire | |
| parent | soundwire: intel: fix alignment issues (diff) | |
| download | kernel-qcow2-linux-7cc6e315317fe3a077fa474941a3ebf93fc15e78.tar.gz kernel-qcow2-linux-7cc6e315317fe3a077fa474941a3ebf93fc15e78.tar.xz kernel-qcow2-linux-7cc6e315317fe3a077fa474941a3ebf93fc15e78.zip | |
soundwire: intel: protect macro parameters
Extra parentheses required here
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/soundwire')
| -rw-r--r-- | drivers/soundwire/intel.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index 56d6c1dda0ff..8c653a563534 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -24,18 +24,18 @@ #define SDW_SHIM_IPPTR 0x8 #define SDW_SHIM_SYNC 0xC -#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * x) -#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * x) -#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * x) -#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * x) -#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * x) -#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * x) - -#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * x) + (0x2 * y)) -#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * x) + (0x2 * y)) -#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * x) -#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * x) -#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * x) +#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) +#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) +#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) +#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) +#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) +#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) + +#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) +#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) +#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) +#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) +#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) #define SDW_SHIM_WAKEEN 0x190 #define SDW_SHIM_WAKESTS 0x192 @@ -82,7 +82,7 @@ #define SDW_SHIM_WAKESTS_STATUS BIT(0) /* Intel ALH Register definitions */ -#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * x)) +#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) |