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| author | Greg Kroah-Hartman | 2010-10-05 19:14:26 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2010-10-05 19:14:26 +0200 |
| commit | e868ab037f86a0143e9dd6d20e32e34ce9454040 (patch) | |
| tree | fc13a9900b36de096170c8baaed0a26919210096 /drivers/staging/brcm80211/phy/wlc_phy_lcn.h | |
| parent | Staging: brcm80211: brcmfmac: s/uint8/u8/ (diff) | |
| download | kernel-qcow2-linux-e868ab037f86a0143e9dd6d20e32e34ce9454040.tar.gz kernel-qcow2-linux-e868ab037f86a0143e9dd6d20e32e34ce9454040.tar.xz kernel-qcow2-linux-e868ab037f86a0143e9dd6d20e32e34ce9454040.zip | |
Staging: brcm80211: phy: s/uint8/u8/
Replace uint8 with u8, the correct kernel type to be using here.
Cc: Brett Rudley <brudley@broadcom.com>
Cc: Henry Ptasinski <henryp@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/brcm80211/phy/wlc_phy_lcn.h')
| -rw-r--r-- | drivers/staging/brcm80211/phy/wlc_phy_lcn.h | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h index e278a2c3d8fe..dc7a79c1687a 100644 --- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h +++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h @@ -21,42 +21,42 @@ struct phy_info_lcnphy { int lcnphy_txrf_sp_9_override; - uint8 lcnphy_full_cal_channel; - uint8 lcnphy_cal_counter; + u8 lcnphy_full_cal_channel; + u8 lcnphy_cal_counter; uint16 lcnphy_cal_temper; bool lcnphy_recal; - uint8 lcnphy_rc_cap; + u8 lcnphy_rc_cap; uint32 lcnphy_mcs20_po; - uint8 lcnphy_tr_isolation_mid; - uint8 lcnphy_tr_isolation_low; - uint8 lcnphy_tr_isolation_hi; + u8 lcnphy_tr_isolation_mid; + u8 lcnphy_tr_isolation_low; + u8 lcnphy_tr_isolation_hi; - uint8 lcnphy_bx_arch; - uint8 lcnphy_rx_power_offset; - uint8 lcnphy_rssi_vf; - uint8 lcnphy_rssi_vc; - uint8 lcnphy_rssi_gs; - uint8 lcnphy_tssi_val; - uint8 lcnphy_rssi_vf_lowtemp; - uint8 lcnphy_rssi_vc_lowtemp; - uint8 lcnphy_rssi_gs_lowtemp; + u8 lcnphy_bx_arch; + u8 lcnphy_rx_power_offset; + u8 lcnphy_rssi_vf; + u8 lcnphy_rssi_vc; + u8 lcnphy_rssi_gs; + u8 lcnphy_tssi_val; + u8 lcnphy_rssi_vf_lowtemp; + u8 lcnphy_rssi_vc_lowtemp; + u8 lcnphy_rssi_gs_lowtemp; - uint8 lcnphy_rssi_vf_hightemp; - uint8 lcnphy_rssi_vc_hightemp; - uint8 lcnphy_rssi_gs_hightemp; + u8 lcnphy_rssi_vf_hightemp; + u8 lcnphy_rssi_vc_hightemp; + u8 lcnphy_rssi_gs_hightemp; int16 lcnphy_pa0b0; int16 lcnphy_pa0b1; int16 lcnphy_pa0b2; uint16 lcnphy_rawtempsense; - uint8 lcnphy_measPower; - uint8 lcnphy_tempsense_slope; - uint8 lcnphy_freqoffset_corr; - uint8 lcnphy_tempsense_option; - uint8 lcnphy_tempcorrx; + u8 lcnphy_measPower; + u8 lcnphy_tempsense_slope; + u8 lcnphy_freqoffset_corr; + u8 lcnphy_tempsense_option; + u8 lcnphy_tempcorrx; bool lcnphy_iqcal_swp_dis; bool lcnphy_hw_iqcal_en; uint lcnphy_bandedge_corr; @@ -85,14 +85,14 @@ struct phy_info_lcnphy { uint16 lcnphy_Very_Low_Gain_db; int8 lcnphy_lastsensed_temperature; int8 lcnphy_pkteng_rssi_slope; - uint8 lcnphy_saved_tx_user_target[TXP_NUM_RATES]; - uint8 lcnphy_volt_winner; - uint8 lcnphy_volt_low; - uint8 lcnphy_54_48_36_24mbps_backoff; - uint8 lcnphy_11n_backoff; - uint8 lcnphy_lowerofdm; - uint8 lcnphy_cck; - uint8 lcnphy_psat_2pt3_detected; + u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES]; + u8 lcnphy_volt_winner; + u8 lcnphy_volt_low; + u8 lcnphy_54_48_36_24mbps_backoff; + u8 lcnphy_11n_backoff; + u8 lcnphy_lowerofdm; + u8 lcnphy_cck; + u8 lcnphy_psat_2pt3_detected; int32 lcnphy_lowest_Re_div_Im; int8 lcnphy_final_papd_cal_idx; uint16 lcnphy_extstxctrl4; @@ -102,19 +102,19 @@ struct phy_info_lcnphy { int16 lcnphy_ofdm_dig_filt_type; lcnphy_cal_results_t lcnphy_cal_results; - uint8 lcnphy_psat_pwr; - uint8 lcnphy_psat_indx; + u8 lcnphy_psat_pwr; + u8 lcnphy_psat_indx; int32 lcnphy_min_phase; - uint8 lcnphy_final_idx; - uint8 lcnphy_start_idx; - uint8 lcnphy_current_index; + u8 lcnphy_final_idx; + u8 lcnphy_start_idx; + u8 lcnphy_current_index; uint16 lcnphy_logen_buf_1; uint16 lcnphy_local_ovr_2; uint16 lcnphy_local_oval_6; uint16 lcnphy_local_oval_5; uint16 lcnphy_logen_mixer_1; - uint8 lcnphy_aci_stat; + u8 lcnphy_aci_stat; uint lcnphy_aci_start_time; int8 lcnphy_tx_power_offset[TXP_NUM_RATES]; }; |