staging: brcm80211: remove OSL_DELAY

and use udelay and mdelay instead

Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

8 files changed, 32 insertions, 43 deletions

diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
index d4e9187508af..b3e2f854bfbf 100644
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ b/drivers/staging/brcm80211/util/aiutils.c
@@ -591,10 +591,10 @@ void ai_core_disable(si_t *sih, u32 bits)
 
 	W_REG(sii->osh, &ai->ioctrl, bits);
 	dummy = R_REG(sii->osh, &ai->ioctrl);
-	OSL_DELAY(10);
+	udelay(10);
 
 	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
-	OSL_DELAY(1);
+	udelay(1);
 }
 
 /* reset and re-enable a core
@@ -623,11 +623,11 @@ void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
 	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
 	dummy = R_REG(sii->osh, &ai->ioctrl);
 	W_REG(sii->osh, &ai->resetctrl, 0);
-	OSL_DELAY(1);
+	udelay(1);
 
 	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
 	dummy = R_REG(sii->osh, &ai->ioctrl);
-	OSL_DELAY(1);
+	udelay(1);
 }
 
 void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
index 91f70e4ce67c..d44157ed0057 100644
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ b/drivers/staging/brcm80211/util/bcmotp.c
@@ -695,7 +695,7 @@ static void *hndotp_init(si_t *sih)
 			    (clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
 			W_REG(osh, &cc->clkdiv, clkdiv);
 		}
-		OSL_DELAY(10);
+		udelay(10);
 
 		ret = (void *)oi;
 	}
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
index 716ef25236bd..6f26abc196be 100644
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ b/drivers/staging/brcm80211/util/hnddma.c
@@ -1004,7 +1004,7 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di)
 #if defined(__mips__)
 	if (!len) {
 		while (!(len = *(u16 *) OSL_UNCACHED(PKTDATA(head))))
-			OSL_DELAY(1);
+			udelay(1);
 
 		*(u16 *) PKTDATA(head) = htol16((u16) len);
 	}
@@ -1599,7 +1599,7 @@ static bool dma32_txreset(dma_info_t *di)
 		  XS_XS_DISABLED), 10000);
 
 	/* wait for the last transaction to complete */
-	OSL_DELAY(300);
+	udelay(300);
 
 	return status == XS_XS_DISABLED;
 }
@@ -1649,7 +1649,7 @@ static bool dma32_txsuspendedidle(dma_info_t *di)
 	if ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
 		return 0;
 
-	OSL_DELAY(2);
+	udelay(2);
 	return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
 		XS_XS_IDLE);
 }
@@ -2162,7 +2162,7 @@ static bool dma64_txreset(dma_info_t *di)
 		  != D64_XS0_XS_DISABLED), 10000);
 
 	/* wait for the last transaction to complete */
-	OSL_DELAY(300);
+	udelay(300);
 
 	return status == D64_XS0_XS_DISABLED;
 }
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
index 8ffb2355e455..f8deb1c51607 100644
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ b/drivers/staging/brcm80211/util/hndpmu.c
@@ -863,7 +863,7 @@ void si_pmu_res_init(si_t *sih, osl_t *osh)
 	}
 
 	/* Add some delay; allow resources to come up and settle. */
-	OSL_DELAY(2000);
+	mdelay(2);
 
 	/* Return to original core */
 	si_setcoreidx(sih, origidx);
@@ -1295,13 +1295,13 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
 		AND_REG(osh, &cc->max_res_mask,
 			~(PMURES_BIT(RES4319_HT_AVAIL)));
 
-		OSL_DELAY(100);
+		udelay(100);
 		AND_REG(osh, &cc->min_res_mask,
 			~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
 		AND_REG(osh, &cc->max_res_mask,
 			~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
 
-		OSL_DELAY(100);
+		udelay(100);
 		SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
 			 PMU_MAX_TRANSITION_DLY);
 		ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
@@ -1317,7 +1317,7 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
 		AND_REG(osh, &cc->max_res_mask,
 			~(PMURES_BIT(RES4336_HT_AVAIL) |
 			  PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
-		OSL_DELAY(100);
+		udelay(100);
 		SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
 			 PMU_MAX_TRANSITION_DLY);
 		ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
@@ -1330,7 +1330,7 @@ static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 xtal)
 		AND_REG(osh, &cc->max_res_mask,
 			~(PMURES_BIT(RES4330_HT_AVAIL) |
 			  PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
-		OSL_DELAY(100);
+		udelay(100);
 		SPINWAIT(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL,
 			 PMU_MAX_TRANSITION_DLY);
 		ASSERT(!(R_REG(osh, &cc->clk_ctl_st) & CCS_HTAVAIL));
@@ -1854,7 +1854,7 @@ u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh)
 		chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
 		ASSERT(cc != NULL);
 		start = R_REG(osh, &cc->pmutimer);
-		OSL_DELAY(ILP_CALC_DUR * 1000);
+		mdelay(ILP_CALC_DUR);
 		end = R_REG(osh, &cc->pmutimer);
 		delta = end - start;
 		ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
@@ -2642,7 +2642,7 @@ u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh)
 		      1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
 
 		/* Delay for well over 4 ILP clocks */
-		OSL_DELAY(1000);
+		udelay(1000);
 
 		/* Read the latched number of ALP ticks per 4 ILP ticks */
 		ilp_ctr =
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c
index 0ae9fbc66730..6616174a3092 100644
--- a/drivers/staging/brcm80211/util/linux_osl.c
+++ b/drivers/staging/brcm80211/util/linux_osl.c
@@ -591,17 +591,6 @@ void osl_assert(char *exp, char *file, int line)
 }
 #endif				/* defined(BCMDBG_ASSERT) */
 
-void osl_delay(uint usec)
-{
-	uint d;
-
-	while (usec > 0) {
-		d = min(usec, (uint)1000);
-		udelay(d);
-		usec -= d;
-	}
-}
-
 #if defined(BCMSDIO) && !defined(BRCM_FULLMAC)
 u8 osl_readb(osl_t *osh, volatile u8 *r)
 {
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index 09c2e10d8e2a..3a73c826d1ef 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -103,7 +103,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi);
 	} while (0)
 
 /* delay needed between the mdio control/ mdiodata register data access */
-#define PR28829_DELAY() OSL_DELAY(10)
+#define PR28829_DELAY() udelay(10)
 
 /* Initialize the PCI core. It's caller's responsibility to make sure that this is done
  * only once
@@ -281,7 +281,7 @@ static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
 		    MDIOCTL_ACCESS_DONE) {
 			break;
 		}
-		OSL_DELAY(1000);
+		udelay(1000);
 		i++;
 	}
 
@@ -342,7 +342,7 @@ pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
 			W_REG(pi->osh, (&pcieregs->mdiocontrol), 0);
 			return 0;
 		}
-		OSL_DELAY(1000);
+		udelay(1000);
 		i++;
 	}
 
diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c
index 65519383f7b6..7b07513f0daf 100644
--- a/drivers/staging/brcm80211/util/sbutils.c
+++ b/drivers/staging/brcm80211/util/sbutils.c
@@ -477,7 +477,7 @@ void sb_core_disable(si_t *sih, u32 bits)
 	   (preserve core-specific bits) */
 	OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
 	dummy = R_SBREG(sii, &sb->sbtmstatelow);
-	OSL_DELAY(1);
+	udelay(1);
 	SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
 		SI_ERROR(("%s: target state still busy\n", __func__));
@@ -485,7 +485,7 @@ void sb_core_disable(si_t *sih, u32 bits)
 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
 		OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
 		dummy = R_SBREG(sii, &sb->sbimstate);
-		OSL_DELAY(1);
+		udelay(1);
 		SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
 	}
 
@@ -494,7 +494,7 @@ void sb_core_disable(si_t *sih, u32 bits)
 		(((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
 		 SBTML_REJ | SBTML_RESET));
 	dummy = R_SBREG(sii, &sb->sbtmstatelow);
-	OSL_DELAY(10);
+	udelay(10);
 
 	/* don't forget to clear the initiator reject bit */
 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
@@ -504,7 +504,7 @@ disable:
 	/* leave reset and reject asserted */
 	W_SBREG(sii, &sb->sbtmstatelow,
 		((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
-	OSL_DELAY(1);
+	udelay(1);
 }
 
 /* reset and re-enable a core
@@ -538,7 +538,7 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
 		(((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
 		  SBTML_SICF_SHIFT) | SBTML_RESET));
 	dummy = R_SBREG(sii, &sb->sbtmstatelow);
-	OSL_DELAY(1);
+	udelay(1);
 
 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR)
 		W_SBREG(sii, &sb->sbtmstatehigh, 0);
@@ -552,13 +552,13 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
 		((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
 		 SBTML_SICF_SHIFT));
 	dummy = R_SBREG(sii, &sb->sbtmstatelow);
-	OSL_DELAY(1);
+	udelay(1);
 
 	/* leave clock enabled */
 	W_SBREG(sii, &sb->sbtmstatelow,
 		((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
 	dummy = R_SBREG(sii, &sb->sbtmstatelow);
-	OSL_DELAY(1);
+	udelay(1);
 }
 
 u32 sb_base(u32 admatch)
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index 963dc3fc6153..ad74552870d0 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -152,7 +152,7 @@ static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
 				bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
 						 SBSDIO_FUNC1_CHIPCLKCSR,
 						 clkset, &err);
-				OSL_DELAY(65);
+				udelay(65);
 			}
 		}
 
@@ -607,7 +607,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
 			W_REG(osh, &cc->clkdiv, clkdiv);
 			SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
 		}
-		OSL_DELAY(10);
+		udelay(10);
 	}
 
 	/* Init nvram from flash if it exists */
@@ -1308,7 +1308,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
 						     sizeof(u32), out);
 				OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
 						     sizeof(u32), outen);
-				OSL_DELAY(XTAL_ON_DELAY);
+				udelay(XTAL_ON_DELAY);
 			}
 
 			/* turn pll on */
@@ -1316,7 +1316,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
 				out &= ~PCI_CFG_GPIO_PLL;
 				OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
 						     sizeof(u32), out);
-				OSL_DELAY(2000);
+				mdelay(2);
 			}
 		} else {
 			if (what & XTAL)
@@ -1416,7 +1416,7 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
 				  == 0), PMU_MAX_TRANSITION_DLY);
 			ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
 		} else {
-			OSL_DELAY(PLL_DELAY);
+			udelay(PLL_DELAY);
 		}
 		break;
 
@@ -2018,6 +2018,6 @@ void si_otp_power(si_t *sih, bool on)
 {
 	if (PMUCTL_ENAB(sih))
 		si_pmu_otp_power(sih, si_osh(sih), on);
-	OSL_DELAY(1000);
+	udelay(1000);
 }