diff options
| author | Dean Luick | 2016-01-11 19:04:33 +0100 |
|---|---|---|
| committer | Doug Ledford | 2016-03-01 16:36:10 +0100 |
| commit | a06e825a13c363da31936d04645e94b99aeb34e2 (patch) | |
| tree | 9d4375d7e77fb5aec5aa1aae0c31d12bf71930fe /drivers/staging/rdma/hfi1/chip_registers.h | |
| parent | staging/hfi1: add dd_dev_dbg (diff) | |
| download | kernel-qcow2-linux-a06e825a13c363da31936d04645e94b99aeb34e2.tar.gz kernel-qcow2-linux-a06e825a13c363da31936d04645e94b99aeb34e2.tar.xz kernel-qcow2-linux-a06e825a13c363da31936d04645e94b99aeb34e2.zip | |
staging/hfi1: set Gen3 half-swing for integrated devices
Correctly set half-swing for integrated devices. A0 needs all fields set for
CcePcieCtrl. B0 and later only need a few fields set.
Reviewed-by: Stuart Summers <john.s.summers@intel.com>
Signed-off-by: Dean Luick <dean.luick@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'drivers/staging/rdma/hfi1/chip_registers.h')
| -rw-r--r-- | drivers/staging/rdma/hfi1/chip_registers.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/staging/rdma/hfi1/chip_registers.h b/drivers/staging/rdma/hfi1/chip_registers.h index 701e9e1012a6..014d7a609ea0 100644 --- a/drivers/staging/rdma/hfi1/chip_registers.h +++ b/drivers/staging/rdma/hfi1/chip_registers.h @@ -551,6 +551,17 @@ #define CCE_MSIX_TABLE_UPPER (CCE + 0x000000100008) #define CCE_MSIX_TABLE_UPPER_RESETCSR 0x0000000100000000ull #define CCE_MSIX_VEC_CLR_WITHOUT_INT (CCE + 0x000000110400) +#define CCE_PCIE_CTRL (CCE + 0x0000000000C0) +#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 0x3ull +#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 0 +#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 0xFull +#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 2 +#define CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 8 +#define CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 9 +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 0x1ull +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 12 +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 0x7ull +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 13 #define CCE_REVISION (CCE + 0x000000000000) #define CCE_REVISION2 (CCE + 0x000000000008) #define CCE_REVISION2_HFI_ID_MASK 0x1ull |