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| author | Gilad Ben-Yossef | 2017-11-13 15:45:36 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2017-11-27 09:20:39 +0100 |
| commit | 2712dc7b01ec4f76a9aef60699bc4d896e75c427 (patch) | |
| tree | 28c85ac8f98a5992005a3aed6773f6cc77586f5e /drivers/staging | |
| parent | staging: ccree: remove unneeded cast (diff) | |
| download | kernel-qcow2-linux-2712dc7b01ec4f76a9aef60699bc4d896e75c427.tar.gz kernel-qcow2-linux-2712dc7b01ec4f76a9aef60699bc4d896e75c427.tar.xz kernel-qcow2-linux-2712dc7b01ec4f76a9aef60699bc4d896e75c427.zip | |
staging: ccree: make mem barrier per request
The driver was issuing a write memory barrier per each
HW descriptor written but these descriptors are written
in groups and we really only need one per group.
White at it, document memory barrier reason.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/ccree/ssi_request_mgr.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index e23c6561a6b1..f5041f71af5a 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -172,7 +172,6 @@ static inline void enqueue_seq( writel_relaxed(seq[i].word[2], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); writel_relaxed(seq[i].word[3], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); writel_relaxed(seq[i].word[4], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); - wmb(); writel_relaxed(seq[i].word[5], (cc_base + CC_REG(DSCRPTR_QUEUE_WORD0))); #ifdef DX_DUMP_DESCS dev_dbg(dev, "desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", @@ -359,6 +358,12 @@ int send_request( #ifdef FLUSH_CACHE_ALL flush_cache_all(); #endif + /* + * We are about to push command to the HW via the command registers + * that may refernece hsot memory. We need to issue a memory barrier + * to make sure there are no outstnading memory writes + */ + wmb(); /* STAT_PHASE_4: Push sequence */ enqueue_seq(cc_base, iv_seq, iv_seq_len); @@ -417,6 +422,12 @@ int send_request_init( set_queue_last_ind(&desc[(len - 1)]); + /* + * We are about to push command to the HW via the command registers + * that may refernece hsot memory. We need to issue a memory barrier + * to make sure there are no outstnading memory writes + */ + wmb(); enqueue_seq(cc_base, desc, len); /* Update the free slots in HW queue */ |