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| author | Amit Daniel Kachhap | 2013-06-24 12:50:43 +0200 |
|---|---|---|
| committer | Eduardo Valentin | 2013-08-13 15:52:03 +0200 |
| commit | a0395eee7ca19623f69f067cc8cfbd4385d85dad (patch) | |
| tree | 4134b00db51d7af53b7257334db9f376fdf083ea /drivers/thermal/samsung/exynos_tmu_data.h | |
| parent | thermal: exynos: Add support to access common register for multistance (diff) | |
| download | kernel-qcow2-linux-a0395eee7ca19623f69f067cc8cfbd4385d85dad.tar.gz kernel-qcow2-linux-a0395eee7ca19623f69f067cc8cfbd4385d85dad.tar.xz kernel-qcow2-linux-a0395eee7ca19623f69f067cc8cfbd4385d85dad.zip | |
thermal: exynos: Add driver support for exynos5440 TMU sensor
This patch modifies TMU controller to add changes needed to work with
exynos5440 platform. This sensor registers 3 instance of the tmu controller
with the thermal zone and hence reports 3 temperature output. This controller
supports upto five trip points. For critical threshold the driver uses the
core driver thermal framework for shutdown.
Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Jungseok Lee <jays.lee@samsung.com>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Acked-by: Eduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
Diffstat (limited to 'drivers/thermal/samsung/exynos_tmu_data.h')
| -rw-r--r-- | drivers/thermal/samsung/exynos_tmu_data.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h index 139dbbb1e264..ad263e9bb58f 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.h +++ b/drivers/thermal/samsung/exynos_tmu_data.h @@ -93,6 +93,42 @@ #define EXYNOS_MAX_TRIGGER_PER_REG 4 +/*exynos5440 specific registers*/ +#define EXYNOS5440_TMU_S0_7_TRIM 0x000 +#define EXYNOS5440_TMU_S0_7_CTRL 0x020 +#define EXYNOS5440_TMU_S0_7_DEBUG 0x040 +#define EXYNOS5440_TMU_S0_7_STATUS 0x060 +#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 +#define EXYNOS5440_TMU_S0_7_TH0 0x110 +#define EXYNOS5440_TMU_S0_7_TH1 0x130 +#define EXYNOS5440_TMU_S0_7_TH2 0x150 +#define EXYNOS5440_TMU_S0_7_EVTEN 0x1F0 +#define EXYNOS5440_TMU_S0_7_IRQEN 0x210 +#define EXYNOS5440_TMU_S0_7_IRQ 0x230 +/* exynos5440 common registers */ +#define EXYNOS5440_TMU_IRQ_STATUS 0x000 +#define EXYNOS5440_TMU_PMIN 0x004 +#define EXYNOS5440_TMU_TEMP 0x008 + +#define EXYNOS5440_TMU_RISE_INT_MASK 0xf +#define EXYNOS5440_TMU_RISE_INT_SHIFT 0 +#define EXYNOS5440_TMU_FALL_INT_MASK 0xf +#define EXYNOS5440_TMU_FALL_INT_SHIFT 4 +#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 +#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 +#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 +#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 +#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 +#define EXYNOS5440_TMU_INTEN_FALL1_SHIFT 5 +#define EXYNOS5440_TMU_INTEN_FALL2_SHIFT 6 +#define EXYNOS5440_TMU_INTEN_FALL3_SHIFT 7 +#define EXYNOS5440_TMU_TH_RISE0_SHIFT 0 +#define EXYNOS5440_TMU_TH_RISE1_SHIFT 8 +#define EXYNOS5440_TMU_TH_RISE2_SHIFT 16 +#define EXYNOS5440_TMU_TH_RISE3_SHIFT 24 +#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 +#define EXYNOS5440_EFUSE_SWAP_OFFSET 8 + #if defined(CONFIG_CPU_EXYNOS4210) extern struct exynos_tmu_init_data const exynos4210_default_tmu_data; #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data) |