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authorGregory Herrero2015-09-22 15:16:49 +0200
committerFelipe Balbi2015-10-01 19:40:17 +0200
commitcad73da26cb9392db3449ab35e506ea13efd1888 (patch)
tree411e20bd135d8d2a3fad658390f68d7aceb7acb5 /drivers/usb/dwc2
parentusb: dwc2: host: disable interrupt during stop (diff)
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usb: dwc2: host: clear pending interrupts prior hibernation
If an interrupt rises during hibernation process, dwc2 will assert interrupt line to interrupt controller. If interrupt is level sensitive, interrupt handler will be called in a loop because dwc2 will not be able to clear it while controller is hibernated. Thus, clear all controller interrupts before hibernation entry. Signed-off-by: Gregory Herrero <gregory.herrero@intel.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Tested-by: John Youn <johnyoun@synopsys.com> Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc2')
-rw-r--r--drivers/usb/dwc2/core.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c5e0a45c565d..bf5e951fbb7f 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -398,6 +398,12 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
}
}
+ /*
+ * Clear any pending interrupts since dwc2 will not be able to
+ * clear them after entering hibernation.
+ */
+ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
+
/* Put the controller in low power state */
pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);