diff options
| author | Chunfeng Yun | 2016-10-19 04:28:24 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2016-10-27 17:02:41 +0200 |
| commit | a29de31b9ed37ebc905fe8580506b93f28701e67 (patch) | |
| tree | 584d3dd402441d93caf9e1700790278ed251b235 /drivers/usb/mtu3/mtu3_hw_regs.h | |
| parent | usb: Add MediaTek USB3 DRD driver (diff) | |
| download | kernel-qcow2-linux-a29de31b9ed37ebc905fe8580506b93f28701e67.tar.gz kernel-qcow2-linux-a29de31b9ed37ebc905fe8580506b93f28701e67.tar.xz kernel-qcow2-linux-a29de31b9ed37ebc905fe8580506b93f28701e67.zip | |
usb: mtu3: Super-Speed Peripheral mode support
add super-speed funtion for peripheral mode
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/mtu3/mtu3_hw_regs.h')
| -rw-r--r-- | drivers/usb/mtu3/mtu3_hw_regs.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h index 08c83c5f6109..212367295276 100644 --- a/drivers/usb/mtu3/mtu3_hw_regs.h +++ b/drivers/usb/mtu3/mtu3_hw_regs.h @@ -260,13 +260,46 @@ /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/ +#define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010) #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C) +#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C) +#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140) + /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/ +/* U3D_LTSSM_CTRL */ +#define FORCE_POLLING_FAIL BIT(4) +#define FORCE_RXDETECT_FAIL BIT(3) +#define SOFT_U3_EXIT_EN BIT(2) +#define COMPLIANCE_EN BIT(1) +#define U1_GO_U2_EN BIT(0) + /* U3D_USB3_CONFIG */ #define USB3_EN BIT(0) +/* U3D_LTSSM_INTR_ENABLE */ +/* U3D_LTSSM_INTR */ +#define U3_RESUME_INTR BIT(18) +#define U3_LFPS_TMOUT_INTR BIT(17) +#define VBUS_FALL_INTR BIT(16) +#define VBUS_RISE_INTR BIT(15) +#define RXDET_SUCCESS_INTR BIT(14) +#define EXIT_U3_INTR BIT(13) +#define EXIT_U2_INTR BIT(12) +#define EXIT_U1_INTR BIT(11) +#define ENTER_U3_INTR BIT(10) +#define ENTER_U2_INTR BIT(9) +#define ENTER_U1_INTR BIT(8) +#define ENTER_U0_INTR BIT(7) +#define RECOVERY_INTR BIT(6) +#define WARM_RST_INTR BIT(5) +#define HOT_RST_INTR BIT(4) +#define LOOPBACK_INTR BIT(3) +#define COMPLIANCE_INTR BIT(2) +#define SS_DISABLE_INTR BIT(1) +#define SS_INACTIVE_INTR BIT(0) + /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/ #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C) |