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| author | Archit Taneja | 2012-05-07 15:20:28 +0200 |
|---|---|---|
| committer | Tomi Valkeinen | 2012-05-09 12:43:05 +0200 |
| commit | 9b9c457b43a0bfe227c5016606a2543e2ac4424e (patch) | |
| tree | 52dc3977a8c6f7dc3625e4f3025df6cd85a2bf3f /drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |
| parent | OMAPDSS: HDMI: Fix ti_hdmi_4xxx_core_dump (diff) | |
| download | kernel-qcow2-linux-9b9c457b43a0bfe227c5016606a2543e2ac4424e.tar.gz kernel-qcow2-linux-9b9c457b43a0bfe227c5016606a2543e2ac4424e.tar.xz kernel-qcow2-linux-9b9c457b43a0bfe227c5016606a2543e2ac4424e.zip | |
OMAPDSS: HDMI: define and dump CORE registers in correct order
The HDMI core register offset macros aren't defined in ascending order of their
values, some of the offset macros are also redefined. The same issues occur when
these core registers are dumped.
Clean up the ordering of HDMI core registers and remove repeated registers in
the definition in ti_hdmi_4xxx_ip.h and in ti_hdmi_4xxx_core_dump().
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c')
| -rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 70 |
1 files changed, 33 insertions, 37 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index e266b8e1aa9f..35f59e47d7fe 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c @@ -900,6 +900,13 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) DUMPCORE(HDMI_CORE_SYS_SRST); DUMPCORE(HDMI_CORE_CTRL1); DUMPCORE(HDMI_CORE_SYS_SYS_STAT); + DUMPCORE(HDMI_CORE_SYS_DE_DLY); + DUMPCORE(HDMI_CORE_SYS_DE_CTRL); + DUMPCORE(HDMI_CORE_SYS_DE_TOP); + DUMPCORE(HDMI_CORE_SYS_DE_CNTL); + DUMPCORE(HDMI_CORE_SYS_DE_CNTH); + DUMPCORE(HDMI_CORE_SYS_DE_LINL); + DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); DUMPCORE(HDMI_CORE_SYS_VID_ACEN); DUMPCORE(HDMI_CORE_SYS_VID_MODE); DUMPCORE(HDMI_CORE_SYS_INTR_STATE); @@ -909,49 +916,15 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) DUMPCORE(HDMI_CORE_SYS_INTR4); DUMPCORE(HDMI_CORE_SYS_UMASK1); DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); - DUMPCORE(HDMI_CORE_SYS_DE_DLY); - DUMPCORE(HDMI_CORE_SYS_DE_CTRL); - DUMPCORE(HDMI_CORE_SYS_DE_TOP); - DUMPCORE(HDMI_CORE_SYS_DE_CNTL); - DUMPCORE(HDMI_CORE_SYS_DE_CNTH); - DUMPCORE(HDMI_CORE_SYS_DE_LINL); - DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); - DUMPCORE(HDMI_CORE_DDC_CMD); - DUMPCORE(HDMI_CORE_DDC_STATUS); DUMPCORE(HDMI_CORE_DDC_ADDR); + DUMPCORE(HDMI_CORE_DDC_SEGM); DUMPCORE(HDMI_CORE_DDC_OFFSET); DUMPCORE(HDMI_CORE_DDC_COUNT1); DUMPCORE(HDMI_CORE_DDC_COUNT2); + DUMPCORE(HDMI_CORE_DDC_STATUS); + DUMPCORE(HDMI_CORE_DDC_CMD); DUMPCORE(HDMI_CORE_DDC_DATA); - DUMPCORE(HDMI_CORE_DDC_SEGM); - - DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); - DUMPCOREAV(HDMI_CORE_AV_DPD); - DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); - DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); - DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); - DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); - DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); - DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); - - for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); - - for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); - - for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); - - for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); - - for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); - - for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) - DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); @@ -991,19 +964,42 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); + + for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); + DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); + + for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); + DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); + + for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); + DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); + + for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); + + for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); + DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); + + for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) + DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); + DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); } |