diff options
| author | Archit Taneja | 2012-06-24 09:38:10 +0200 |
|---|---|---|
| committer | Tomi Valkeinen | 2012-06-29 09:15:53 +0200 |
| commit | cc937e5e4bcf6c97746384e5c07dd2b2c45898b3 (patch) | |
| tree | 3481dedbc93da8343c3f5e9622769795b737e833 /drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |
| parent | OMAPFB: Map interlace field in omap_video_timings with fb vmode flags (diff) | |
| download | kernel-qcow2-linux-cc937e5e4bcf6c97746384e5c07dd2b2c45898b3.tar.gz kernel-qcow2-linux-cc937e5e4bcf6c97746384e5c07dd2b2c45898b3.tar.xz kernel-qcow2-linux-cc937e5e4bcf6c97746384e5c07dd2b2c45898b3.zip | |
OMAPDSS: HDMI: Remove custom hdmi_video_timings struct
The hdmi CEA and VESA timings were represented by the struct hdmi_video_timings,
omap_video_timings couldn't be used as it didn't contain the fields hsync/vsync
polarities and interlaced/progressive information.
Remove hdmi_video_timings, and use omap_video_timings instead.
Cc: Mythri P K <mythripk@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c')
| -rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index 49b171b1f4ae..c23b85a20cdc 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c @@ -741,11 +741,15 @@ static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data) { u32 r; + bool vsync_pol, hsync_pol; pr_debug("Enter hdmi_wp_video_config_interface\n"); + vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; + hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); - r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7); - r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6); + r = FLD_MOD(r, vsync_pol, 7, 7); + r = FLD_MOD(r, hsync_pol, 6, 6); r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3); r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); |