diff options
| author | Ricardo Neri | 2012-01-31 20:36:06 +0100 |
|---|---|---|
| committer | Tomi Valkeinen | 2012-02-21 08:40:15 +0100 |
| commit | d8989d96eb35335e4e464369da7bdb28e8c84a9f (patch) | |
| tree | 2f10cc942ab4260f96ac71325ce6cf9b38e93700 /drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |
| parent | OMAPDSS: Add DSS feature for HDMI MCLK for audio (diff) | |
| download | kernel-qcow2-linux-d8989d96eb35335e4e464369da7bdb28e8c84a9f.tar.gz kernel-qcow2-linux-d8989d96eb35335e4e464369da7bdb28e8c84a9f.tar.xz kernel-qcow2-linux-d8989d96eb35335e4e464369da7bdb28e8c84a9f.zip | |
OMAPDSS: HDMI: Implement initialization of MCLK
When the MCLK is used to drive the Audio Clock Regeneration packets,
the initialization procedure is to set ACR_CTRL[2] to 0 and then
back again to 1. Also, devices that do not support the MCLK, use
the TMDS clock directly by leaving ACR_CTRL[2] set to 0.
The MLCK clock divisor, mclk_mode, is configured only if MLCK
is used. Such configuration is no longer related to the CTS mode
as in some silicon revisions CTS SW-mode is used along with the MCLK.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c')
| -rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index b9b97f172cde..bb784d2329b6 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c @@ -1068,13 +1068,9 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data, u32 r; void __iomem *av_base = hdmi_av_base(ip_data); - /* audio clock recovery parameters */ - r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); - r = FLD_MOD(r, cfg->use_mclk, 2, 2); - r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); - r = FLD_MOD(r, cfg->cts_mode, 0, 0); - hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); - + /* + * Parameters for generation of Audio Clock Recovery packets + */ REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); @@ -1086,14 +1082,6 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data, REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); } else { - /* - * HDMI IP uses this configuration to divide the MCLK to - * update CTS value. - */ - REG_FLD_MOD(av_base, - HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); - - /* Configure clock for audio packets */ REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, cfg->aud_par_busclk, 7, 0); REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, @@ -1102,6 +1090,25 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data, (cfg->aud_par_busclk >> 16), 7, 0); } + /* Set ACR clock divisor */ + REG_FLD_MOD(av_base, + HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); + + r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); + /* + * Use TMDS clock for ACR packets. For devices that use + * the MCLK, this is the first part of the MCLK initialization. + */ + r = FLD_MOD(r, 0, 2, 2); + + r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); + r = FLD_MOD(r, cfg->cts_mode, 0, 0); + hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); + + /* For devices using MCLK, this completes its initialization. */ + if (cfg->use_mclk) + REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); + /* Override of SPDIF sample frequency with value in I2S_CHST4 */ REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1); |