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| author | Felipe Balbi | 2018-09-07 08:16:51 +0200 |
|---|---|---|
| committer | Bjorn Helgaas | 2018-09-28 19:47:34 +0200 |
| commit | d6112f8def514e019658bcc9b57d53acdb71ca3f (patch) | |
| tree | 1d2666a9f462e87b0d27038a2c8e15d4a8f8e2dd /drivers | |
| parent | ACPI/PCI: Pay attention to device-specific _PXM node values (diff) | |
| download | kernel-qcow2-linux-d6112f8def514e019658bcc9b57d53acdb71ca3f.tar.gz kernel-qcow2-linux-d6112f8def514e019658bcc9b57d53acdb71ca3f.tar.xz kernel-qcow2-linux-d6112f8def514e019658bcc9b57d53acdb71ca3f.zip | |
PCI: Add support for Immediate Readiness
PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register:
Immediate Readiness – This optional bit, when Set, indicates the Function
is guaranteed to be ready to successfully complete valid configuration
accesses at any time following any reset that the host is capable of
issuing Configuration Requests to this Function.
When this bit is Set, for accesses to this Function, software is exempt
from all requirements to delay configuration accesses following any type
of reset, including but not limited to the timing requirements defined in
Section 6.6.
This means that all delays after a Conventional or Function Reset can be
skipped.
This patch reads such bit and caches its value in a flag inside struct
pci_dev to be checked later if we should delay or can skip delays after a
reset. While at that, also move the explicit msleep(100) call from
pcie_flr() and pci_af_flr() to pci_dev_wait().
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
[bhelgaas: rename PCI_STATUS_IMMEDIATE to PCI_STATUS_IMM_READY]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/pci.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1835f3a7aa8d..ee7c2f4eef9b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -999,7 +999,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) * because have already delayed for the bridge. */ if (dev->runtime_d3cold) { - if (dev->d3cold_delay) + if (dev->d3cold_delay && !dev->imm_ready) msleep(dev->d3cold_delay); /* * When powering on a bridge from D3cold, the @@ -2644,6 +2644,7 @@ EXPORT_SYMBOL_GPL(pci_d3cold_disable); void pci_pm_init(struct pci_dev *dev) { int pm; + u16 status; u16 pmc; pm_runtime_forbid(&dev->dev); @@ -2706,6 +2707,10 @@ void pci_pm_init(struct pci_dev *dev) /* Disable the PME# generation functionality */ pci_pme_active(dev, false); } + + pci_read_config_word(dev, PCI_STATUS, &status); + if (status & PCI_STATUS_IMM_READY) + dev->imm_ready = 1; } static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) @@ -4376,6 +4381,9 @@ int pcie_flr(struct pci_dev *dev) pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); + if (dev->imm_ready) + return 0; + /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within * 100ms, but may silently discard requests while the FLR is in @@ -4417,6 +4425,9 @@ static int pci_af_flr(struct pci_dev *dev, int probe) pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); + if (dev->imm_ready) + return 0; + /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, * updated 27 July 2006; a device must complete an FLR within |