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| author | Murthy, Raghuveer | 2011-03-03 16:27:58 +0100 |
|---|---|---|
| committer | Tomi Valkeinen | 2011-03-11 14:46:29 +0100 |
| commit | 5c6366e14d9d4466ae34a1ccbc08dd8738909c1f (patch) | |
| tree | 8968a2109d82feb21927333c3d85f1fef451d49c /firmware/whiteheat.HEX | |
| parent | HACK: OMAP: DSS2: add delay after enabling clocks (diff) | |
| download | kernel-qcow2-linux-5c6366e14d9d4466ae34a1ccbc08dd8738909c1f.tar.gz kernel-qcow2-linux-5c6366e14d9d4466ae34a1ccbc08dd8738909c1f.tar.xz kernel-qcow2-linux-5c6366e14d9d4466ae34a1ccbc08dd8738909c1f.zip | |
OMAP: DSS2: Adding dss_features for independent core clk divider
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.
In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.
The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'firmware/whiteheat.HEX')
0 files changed, 0 insertions, 0 deletions