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| author | Quinn Jensen | 2007-07-09 23:06:53 +0200 |
|---|---|---|
| committer | Russell King | 2007-07-22 16:44:46 +0200 |
| commit | 52c543f90c4095dff71dc125017594b61a753069 (patch) | |
| tree | 0b88dafea91f1fd2cb44bb863271503e765f7156 /include/asm-arm/arch-mxc/entry-macro.S | |
| parent | [ARM] 4481/1: Fix a bug when i.MX is compiled as a module (diff) | |
| download | kernel-qcow2-linux-52c543f90c4095dff71dc125017594b61a753069.tar.gz kernel-qcow2-linux-52c543f90c4095dff71dc125017594b61a753069.tar.xz kernel-qcow2-linux-52c543f90c4095dff71dc125017594b61a753069.zip | |
[ARM] 4461/1: MXC platform and i.MX31ADS core support
This patch adds the foundation pieces for
the Freescale MXC platforms, including
i.MX2 and i.MX3 based systems.
The bare-bones MX31 support in this patch
boots to the rootdev panic with 8250 serial
console configured "console=ttyS0,115200".
It assumes that Redboot is the boot loader.
Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com>
Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-mxc/entry-macro.S')
| -rw-r--r-- | include/asm-arm/arch-mxc/entry-macro.S | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S new file mode 100644 index 000000000000..b542433afb1b --- /dev/null +++ b/include/asm-arm/arch-mxc/entry-macro.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + @ this macro disables fast irq (not implemented) + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + @ this macro checks which interrupt occured + @ and returns its number in irqnr + @ and returns if an interrupt occured in irqstat + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) + @ Load offset & priority of the highest priority + @ interrupt pending from AVIC_NIVECSR + ldr \irqstat, [\base, #0x40] + @ Shift to get the decoded IRQ number, using ASR so + @ 'no interrupt pending' becomes 0xffffffff + mov \irqnr, \irqstat, asr #16 + @ set zero flag if IRQ + 1 == 0 + adds \tmp, \irqnr, #1 + .endm + + @ irq priority table (not used) + .macro irq_prio_table + .endm |