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| author | Linus Torvalds | 2007-08-31 06:54:57 +0200 |
|---|---|---|
| committer | Linus Torvalds | 2007-08-31 06:54:57 +0200 |
| commit | feabb06bd70551668540f2305047675667f5f60f (patch) | |
| tree | da65dedf73cae1e6fa59f923267a1b25501523a9 /include/asm-arm/plat-s3c/map.h | |
| parent | fix maxcpus=1 oops in show_stat() (diff) | |
| parent | [ARM] 4561/1: i.MX/MX1 GPIO parenthes omission and input setup fix (diff) | |
| download | kernel-qcow2-linux-feabb06bd70551668540f2305047675667f5f60f.tar.gz kernel-qcow2-linux-feabb06bd70551668540f2305047675667f5f60f.tar.xz kernel-qcow2-linux-feabb06bd70551668540f2305047675667f5f60f.zip | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 4561/1: i.MX/MX1 GPIO parenthes omission and input setup fix
[ARM] 4557/1: Fix PXA irq gpio initialization
[ARM] 4551/1: s3c24xx: fix wrong virtual address offsets
[ARM] 4552/1: i.MX/MX1 GPIO output setup fix
[ARM] 4553/1: ARM at91: define FIQ_START
[ARM] 4554/1: replace consistent_sync() with flush_ioremap_region()
ARM: OMAP: Enable serial idling and wakeup features
ARM: OMAP2: Force APLLs always active
ARM: OMAP: H3 workqueue fixes
ARM: OMAP: OSK led fixes
ARM: OMAP: fix OMAP1 dmtimer build warning
ARM: OMAP: Fix 32k timer unsupported one-shot mode
Diffstat (limited to 'include/asm-arm/plat-s3c/map.h')
| -rw-r--r-- | include/asm-arm/plat-s3c/map.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h index 95a82b0e84a1..b84289d32a54 100644 --- a/include/asm-arm/plat-s3c/map.h +++ b/include/asm-arm/plat-s3c/map.h @@ -30,11 +30,11 @@ #define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) #endif -#define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */ -#define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */ +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ #endif /* __ASM_PLAT_MAP_H */ |