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| author | Andrew Isaacson | 2005-10-20 08:56:20 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2005-10-29 20:32:46 +0200 |
| commit | 93ce2f524e96571711029884e6340c790a029b94 (patch) | |
| tree | 1cb69ac513d01b25a2c300c90a2f11c69c0290e9 /include/asm-mips/cpu.h | |
| parent | Sibyte header cleanup (diff) | |
| download | kernel-qcow2-linux-93ce2f524e96571711029884e6340c790a029b94.tar.gz kernel-qcow2-linux-93ce2f524e96571711029884e6340c790a029b94.tar.xz kernel-qcow2-linux-93ce2f524e96571711029884e6340c790a029b94.zip | |
Add support for SB1A CPU.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 46b2a8dc2ee0..48eac296060f 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -93,6 +93,7 @@ */ #define PRID_IMP_SB1 0x0100 +#define PRID_IMP_SB1A 0x1100 /* * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT @@ -194,7 +195,8 @@ #define CPU_AU1200 59 #define CPU_34K 60 #define CPU_PR4450 61 -#define CPU_LAST 61 +#define CPU_SB1A 62 +#define CPU_LAST 62 /* * ISA Level encodings |