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| author | Maciej W. Rozycki | 2006-02-13 10:15:49 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2006-02-14 20:13:25 +0100 |
| commit | 9cf8ff96447f995d5ea18ec9f25dc8dae26501a2 (patch) | |
| tree | 62e9c25e9e471da770500891e8357c85f9070bff /include/asm-mips/cpu.h | |
| parent | [MIPS] RM9000: Fix buggy I-cache workaround. (diff) | |
| download | kernel-qcow2-linux-9cf8ff96447f995d5ea18ec9f25dc8dae26501a2.tar.gz kernel-qcow2-linux-9cf8ff96447f995d5ea18ec9f25dc8dae26501a2.tar.xz kernel-qcow2-linux-9cf8ff96447f995d5ea18ec9f25dc8dae26501a2.zip | |
[MIPS] Fix CPU type bitmasks for MIPS III, IV and V.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 934e063e79f1..818b9a97e214 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -204,9 +204,9 @@ */ #define MIPS_CPU_ISA_I 0x00000001 #define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00000003 -#define MIPS_CPU_ISA_IV 0x00000004 -#define MIPS_CPU_ISA_V 0x00000005 +#define MIPS_CPU_ISA_III 0x00000004 +#define MIPS_CPU_ISA_IV 0x00000008 +#define MIPS_CPU_ISA_V 0x00000010 #define MIPS_CPU_ISA_M32R1 0x00000020 #define MIPS_CPU_ISA_M32R2 0x00000040 #define MIPS_CPU_ISA_M64R1 0x00000080 |