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| author | David S. Miller | 2006-02-02 00:55:21 +0100 |
|---|---|---|
| committer | David S. Miller | 2006-03-20 10:11:32 +0100 |
| commit | 517af33237ecfc3c8a93b335365fa61e741ceca4 (patch) | |
| tree | 58eff40eb4c517c4fd49fd347d38273ee1e1ee4b /include/asm-sparc64/thread_info.h | |
| parent | [SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h (diff) | |
| download | kernel-qcow2-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.tar.gz kernel-qcow2-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.tar.xz kernel-qcow2-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.zip | |
[SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section. The default uses
virtual addresses, and the patch instructions use physical
address load/stores.
We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/thread_info.h')
0 files changed, 0 insertions, 0 deletions