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authorBen Widawsky2012-07-12 20:01:05 +0200
committerDaniel Vetter2012-07-25 18:23:49 +0200
commitc0c7babc48c4f6943ed3070d04630ea3ac9272ee (patch)
tree86067dfb6b57953296e26dbf58ac8d13693c43f3 /include/drm/radeon_drm.h
parentdrm/i915: Reserve ioctl numbers for set/get_caching (diff)
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drm/i915: add register read IOCTL
The interface's immediate purpose is to do synchronous timestamp queries as required by GL_TIMESTAMP. The GPU has a register for reading the timestamp but because that would normally require root access through libpciaccess, the IOCTL can provide this service instead. Currently the implementation whitelists only the render ring timestamp register, because that is the only thing we need to expose at this time. v2: make size implicit based on the register offset Add a generation check Reviewed-by: Eric Anholt <eric@anholt.net> Cc: Jacek Lawrynowicz <jacek.lawrynowicz@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: fixup the ioctl numerb:] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/drm/radeon_drm.h')
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