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authorChen Zhong2017-10-05 05:50:25 +0200
committerStephen Boyd2017-11-02 09:10:11 +0100
commitbda921fad518b4d5d2249d41432025ce5b368173 (patch)
treedbe9fe429e88ed5ff37dec23aa70fa3f3bce0820 /include/dt-bindings/clock/exynos7-clk.h
parentclk: mediatek: add the option for determining PLL source clock (diff)
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clk: mediatek: add clocks dt-bindings required header for MT7622 SoC
Add the required header for the entire clocks dt-bindings exported from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys and audsys which could be found on MT7622 SoC. Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings/clock/exynos7-clk.h')
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