diff options
| author | Stephen Boyd | 2017-06-14 19:36:30 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-06-14 19:36:30 +0200 |
| commit | 7f274d54bb664519e62001a4782f5d5f2c95b06e (patch) | |
| tree | 78a2780a58dee9f6901fc4f00eef44fd2ddb1dab /include/dt-bindings/clock | |
| parent | Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/... (diff) | |
| parent | clk: samsung: exynos542x: Add EPLL rate table (diff) | |
| download | kernel-qcow2-linux-7f274d54bb664519e62001a4782f5d5f2c95b06e.tar.gz kernel-qcow2-linux-7f274d54bb664519e62001a4782f5d5f2c95b06e.tar.xz kernel-qcow2-linux-7f274d54bb664519e62001a4782f5d5f2c95b06e.zip | |
Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki
- conversion to the clk_hw API
- definitions and fixes of exynos5420 SoC audio subsystem
related clocks
* tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos542x: Add EPLL rate table
clk: samsung: Add missing exynos5420 audio related clocks
clk: samsung: Add enable/disable operation for PLL36XX clocks
clk: samsung: s5pv210-audss: Convert to the new clk_hw API
clk: samsung: exynos-clkout: Convert to the new clk_hw API
clk: samsung: exynos-audss: Convert to the new clk_hw API
clk: samsung: Convert common drivers to the new clk_hw API
clk: samsung: Add local variable to match its purpose
clk: samsung: Remove dead code
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 6fd21c291416..2740ae0424a9 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -217,6 +217,9 @@ #define CLK_MOUT_MCLK_CDREX 654 #define CLK_MOUT_BPLL 655 #define CLK_MOUT_MX_MSPLL_CCORE 656 +#define CLK_MOUT_EPLL 657 +#define CLK_MOUT_MAU_EPLL 658 +#define CLK_MOUT_USER_MAU_EPLL 659 /* divider clocks */ #define CLK_DOUT_PIXEL 768 |