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| author | Icenowy Zheng | 2018-05-03 20:38:41 +0200 |
|---|---|---|
| committer | Maxime Ripard | 2018-05-04 17:05:46 +0200 |
| commit | b7c7b05065aa77ae3d7b70b9139ed58970daed78 (patch) | |
| tree | d241bfa4719e5a3020602704a5ed41c00084b8d3 /include/dt-bindings/clock | |
| parent | Linux 4.17-rc1 (diff) | |
| download | kernel-qcow2-linux-b7c7b05065aa77ae3d7b70b9139ed58970daed78.tar.gz kernel-qcow2-linux-b7c7b05065aa77ae3d7b70b9139ed58970daed78.tar.xz kernel-qcow2-linux-b7c7b05065aa77ae3d7b70b9139ed58970daed78.zip | |
clk: sunxi-ng: add support for H6 PRCM CCU
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3
and A64. However, the PRCM CCU is rearranged; the register arragement
is now similar to the main CCU of H6, and the PRCM now has two APB
buses to control -- one is clocked from AHB clock derivde from AR100
clock, the other is clocked from the same mux with AR100 clock.
Therefore a new driver is written for it.
As there's no official document about the PRCM in H6, all the information
are indirectly collected from BSP and parts of the document, and the
information source is noted as comments in the driver's source code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h new file mode 100644 index 000000000000..76136132a13e --- /dev/null +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB2_UART 7 +#define CLK_R_APB2_I2C 8 +#define CLK_R_APB1_IR 9 +#define CLK_R_APB1_W1 10 + +#define CLK_IR 11 +#define CLK_W1 12 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ |