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| author | Dmitry Osipenko | 2018-04-09 21:28:26 +0200 |
|---|---|---|
| committer | Thierry Reding | 2018-04-27 11:21:21 +0200 |
| commit | 5c8d08f3471265dfd2f6db6d381751848dbf7db3 (patch) | |
| tree | e61d63948fd2042401af352a11eee842a5a4f3c2 /include/dt-bindings/memory/tegra124-mc.h | |
| parent | Linux 4.17-rc1 (diff) | |
| download | kernel-qcow2-linux-5c8d08f3471265dfd2f6db6d381751848dbf7db3.tar.gz kernel-qcow2-linux-5c8d08f3471265dfd2f6db6d381751848dbf7db3.tar.xz kernel-qcow2-linux-5c8d08f3471265dfd2f6db6d381751848dbf7db3.zip | |
dt-bindings: memory: tegra: Add hot resets definitions
Add definitions for the Tegra20+ memory controller hot resets.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/memory/tegra124-mc.h')
| -rw-r--r-- | include/dt-bindings/memory/tegra124-mc.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index f534d7c06019..186e6b7e9b35 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -29,4 +29,29 @@ #define TEGRA_SWGROUP_VIC 24 #define TEGRA_SWGROUP_VI 25 +#define TEGRA124_MC_RESET_AFI 0 +#define TEGRA124_MC_RESET_AVPC 1 +#define TEGRA124_MC_RESET_DC 2 +#define TEGRA124_MC_RESET_DCB 3 +#define TEGRA124_MC_RESET_HC 4 +#define TEGRA124_MC_RESET_HDA 5 +#define TEGRA124_MC_RESET_ISP2 6 +#define TEGRA124_MC_RESET_MPCORE 7 +#define TEGRA124_MC_RESET_MPCORELP 8 +#define TEGRA124_MC_RESET_MSENC 9 +#define TEGRA124_MC_RESET_PPCS 10 +#define TEGRA124_MC_RESET_SATA 11 +#define TEGRA124_MC_RESET_VDE 12 +#define TEGRA124_MC_RESET_VI 13 +#define TEGRA124_MC_RESET_VIC 14 +#define TEGRA124_MC_RESET_XUSB_HOST 15 +#define TEGRA124_MC_RESET_XUSB_DEV 16 +#define TEGRA124_MC_RESET_TSEC 17 +#define TEGRA124_MC_RESET_SDMMC1 18 +#define TEGRA124_MC_RESET_SDMMC2 19 +#define TEGRA124_MC_RESET_SDMMC3 20 +#define TEGRA124_MC_RESET_SDMMC4 21 +#define TEGRA124_MC_RESET_ISP2B 22 +#define TEGRA124_MC_RESET_GPU 23 + #endif |