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| author | Stephen Boyd | 2017-01-27 20:53:06 +0100 |
|---|---|---|
| committer | Stephen Boyd | 2017-01-27 20:53:06 +0100 |
| commit | 195559506981c0a4c62397ad0220888324750070 (patch) | |
| tree | e58fc27d85c7d77c29a9b182b18d318040128f72 /include/dt-bindings | |
| parent | Merge tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/... (diff) | |
| parent | clk: samsung: mark s3c...._clk_sleep_init() as __init (diff) | |
| download | kernel-qcow2-linux-195559506981c0a4c62397ad0220888324750070.tar.gz kernel-qcow2-linux-195559506981c0a4c62397ad0220888324750070.tar.xz kernel-qcow2-linux-195559506981c0a4c62397ad0220888324750070.zip | |
Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY
- Exynos PLL code updates and overall minor clean-ups
* tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: mark s3c...._clk_sleep_init() as __init
clk: samsung: Add enable/disable support for PLL35XX clocks
clk: samsung: exynos5433: Correct typos in SoC name
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 |