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authorLiu Ying2013-07-03 09:29:06 +0200
committerShawn Guo2013-07-15 02:28:08 +0200
commit3b79cd15bfc5f1ddb5e387310fa3dbb09b81b552 (patch)
tree85abb902178a907b7629dcf45f092f2ac305ec63 /include/dt-bindings
parentARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX (diff)
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ARM: i.MX6Q: correct emi_sel clock muxing
The correct muxing for emi_sel clock should be 2b'00 - 396M PFD 2b'01 - PLL3 2b'10 - AXI clk root 2b'11 - 352M PFD This patch corrects the muxing in the clock driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
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