diff options
| author | Icenowy Zheng | 2017-03-01 21:13:39 +0100 |
|---|---|---|
| committer | Maxime Ripard | 2017-03-06 10:25:56 +0100 |
| commit | 9be1c8afb4926aee043d48493c0474c0eea56540 (patch) | |
| tree | fdad2e5551a7797318b50937b2ee3c0f5be62677 /include/dt-bindings | |
| parent | clk: sunxi-ng: gate: Support common pre-dividers (diff) | |
| download | kernel-qcow2-linux-9be1c8afb4926aee043d48493c0474c0eea56540.tar.gz kernel-qcow2-linux-9be1c8afb4926aee043d48493c0474c0eea56540.tar.xz kernel-qcow2-linux-9be1c8afb4926aee043d48493c0474c0eea56540.zip | |
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.
Add its support in our existing H3 CCU driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/sun8i-h3-ccu.h | 5 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun8i-h3-ccu.h | 5 |
2 files changed, 8 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index efb7ba2bd515..c2afc41d6964 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -91,7 +91,7 @@ #define CLK_BUS_UART1 63 #define CLK_BUS_UART2 64 #define CLK_BUS_UART3 65 -#define CLK_BUS_SCR 66 +#define CLK_BUS_SCR0 66 #define CLK_BUS_EPHY 67 #define CLK_BUS_DBG 68 @@ -142,4 +142,7 @@ #define CLK_GPU 114 +/* New clocks imported in H5 */ +#define CLK_BUS_SCR1 115 + #endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h index 6b7af80c26ec..484c2a22919d 100644 --- a/include/dt-bindings/reset/sun8i-h3-ccu.h +++ b/include/dt-bindings/reset/sun8i-h3-ccu.h @@ -98,6 +98,9 @@ #define RST_BUS_UART1 50 #define RST_BUS_UART2 51 #define RST_BUS_UART3 52 -#define RST_BUS_SCR 53 +#define RST_BUS_SCR0 53 + +/* New resets imported in H5 */ +#define RST_BUS_SCR1 54 #endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ |