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| author | Marc Zyngier | 2015-06-08 16:37:26 +0200 |
|---|---|---|
| committer | Marc Zyngier | 2015-08-12 12:28:24 +0200 |
| commit | fb182cf84568cc33ab41121bc8cc999f7aacbd47 (patch) | |
| tree | 4f4db678e56aff1dd7953e2936054b455db8355e /include/linux/irqchip/arm-gic-v3.h | |
| parent | KVM: arm/arm64: vgic: Convert struct vgic_lr to use bitfields (diff) | |
| download | kernel-qcow2-linux-fb182cf84568cc33ab41121bc8cc999f7aacbd47.tar.gz kernel-qcow2-linux-fb182cf84568cc33ab41121bc8cc999f7aacbd47.tar.xz kernel-qcow2-linux-fb182cf84568cc33ab41121bc8cc999f7aacbd47.zip | |
KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/linux/irqchip/arm-gic-v3.h')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index ffbc034c8810..cf637d65b589 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -268,9 +268,12 @@ #define ICH_LR_EOI (1UL << 41) #define ICH_LR_GROUP (1UL << 60) +#define ICH_LR_HW (1UL << 61) #define ICH_LR_STATE (3UL << 62) #define ICH_LR_PENDING_BIT (1UL << 62) #define ICH_LR_ACTIVE_BIT (1UL << 63) +#define ICH_LR_PHYS_ID_SHIFT 32 +#define ICH_LR_PHYS_ID_MASK (0x3ffUL << ICH_LR_PHYS_ID_SHIFT) #define ICH_MISR_EOI (1 << 0) #define ICH_MISR_U (1 << 1) |