diff options
| author | Vincent Wan | 2014-11-05 07:09:00 +0100 |
|---|---|---|
| committer | Ulf Hansson | 2014-11-26 14:30:28 +0100 |
| commit | 9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb (patch) | |
| tree | a07d0b69bb64491bee30c2d90e8fa3c24c773797 /include/linux/mmc | |
| parent | mmc: core: use mmc_send_status to check hw_reset (diff) | |
| download | kernel-qcow2-linux-9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb.tar.gz kernel-qcow2-linux-9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb.tar.xz kernel-qcow2-linux-9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb.zip | |
mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: Vincent Wan <vincent.wan@amd.com>
Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Tested-by: Vikram B <vikram.b@amd.com>
Tested-by: Raghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'include/linux/mmc')
| -rw-r--r-- | include/linux/mmc/sdhci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 931ac5e05453..ae7f357b78c9 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -102,6 +102,8 @@ struct sdhci_host { #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) /* Controller does not support 64-bit DMA */ #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) +/* need clear transfer mode register before send cmd */ +#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ |