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| author | Catalin Marinas | 2013-12-05 17:56:50 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2013-12-06 18:21:52 +0100 |
| commit | 2f7dc6027522499582a520807cb9ffda589de47e (patch) | |
| tree | a66a8bbd89cea0bb39e98638d0d805d72dd4a45d /kernel/debug | |
| parent | arm64: kernel: add code to set cpu boot mode to secondary_entry shim (diff) | |
| download | kernel-qcow2-linux-2f7dc6027522499582a520807cb9ffda589de47e.tar.gz kernel-qcow2-linux-2f7dc6027522499582a520807cb9ffda589de47e.tar.xz kernel-qcow2-linux-2f7dc6027522499582a520807cb9ffda589de47e.zip | |
arm64: Fix memory shareability attribute for ioremap_wc/cache
Write-combine and cacheable mappings use Normal memory on arm64. On SMP
systems, the pte needs the shareability bit which is set in
pgprot_default. Use this for defining PROT_DEFAULT used by ioremap_wc
and ioremap_cache (Device memory is shareable by default, does not need
additional attributes).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'kernel/debug')
0 files changed, 0 insertions, 0 deletions