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author | Marc St-Jean | 2007-05-06 23:48:45 +0200 |
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committer | Linus Torvalds | 2007-05-07 21:12:50 +0200 |
commit | beab697ab4b2962e3d741b476abe443baad0933d (patch) | |
tree | f581ce38378f6cacbf0042b4eb9c084a6fc932d9 /mm/highmem.c | |
parent | add new_id to PCMCIA drivers (diff) | |
download | kernel-qcow2-linux-beab697ab4b2962e3d741b476abe443baad0933d.tar.gz kernel-qcow2-linux-beab697ab4b2962e3d741b476abe443baad0933d.tar.xz kernel-qcow2-linux-beab697ab4b2962e3d741b476abe443baad0933d.zip |
serial driver PMC MSP71xx
Serial driver patch for the PMC-Sierra MSP71xx devices.
There are three different fixes:
1 Fix for DesignWare APB THRE errata: In brief, this is a non-standard
16550 in that the THRE interrupt will not re-assert itself simply by
disabling and re-enabling the THRI bit in the IER, it is only re-enabled
if a character is actually sent out.
It appears that the "8250-uart-backup-timer.patch" in the "mm" tree
also fixes it so we have dropped our initial workaround. This patch now
needs to be applied on top of that "mm" patch.
2 Fix for Busy Detect on LCR write: The DesignWare APB UART has a feature
which causes a new Busy Detect interrupt to be generated if it's busy
when the LCR is written. This fix saves the value of the LCR and
rewrites it after clearing the interrupt.
3 Workaround for interrupt/data concurrency issue: The SoC needs to
ensure that writes that can cause interrupts to be cleared reach the UART
before returning from the ISR. This fix reads a non-destructive register
on the UART so the read transaction completion ensures the previously
queued write transaction has also completed.
Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'mm/highmem.c')
0 files changed, 0 insertions, 0 deletions