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| author | Yang Shi | 2016-05-17 01:36:26 +0200 |
|---|---|---|
| committer | David S. Miller | 2016-05-17 20:03:33 +0200 |
| commit | 4c1cd4fdfd14ecd417962f8c2166506132697f7c (patch) | |
| tree | 14fba1a53e6426a3e4c12773dacd5fe81780b3b3 /net/qrtr | |
| parent | asix: Fix offset calculation in asix_rx_fixup() causing slow transmissions (diff) | |
| download | kernel-qcow2-linux-4c1cd4fdfd14ecd417962f8c2166506132697f7c.tar.gz kernel-qcow2-linux-4c1cd4fdfd14ecd417962f8c2166506132697f7c.tar.xz kernel-qcow2-linux-4c1cd4fdfd14ecd417962f8c2166506132697f7c.zip | |
bpf: arm64: remove callee-save registers use for tmp registers
In the current implementation of ARM64 eBPF JIT, R23 and R24 are used for
tmp registers, which are callee-saved registers. This leads to variable size
of JIT prologue and epilogue. The latest blinding constant change prefers to
constant size of prologue and epilogue. AAPCS reserves R9 ~ R15 for temp
registers which not need to be saved/restored during function call. So, replace
R23 and R24 to R10 and R11, and remove tmp_used flag to save 2 instructions for
some jited BPF program.
CC: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Zi Shen Lim <zlim.lnx@gmail.com>
Signed-off-by: Yang Shi <yang.shi@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/qrtr')
0 files changed, 0 insertions, 0 deletions