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| author | Will Deacon | 2013-09-04 13:30:08 +0200 |
|---|---|---|
| committer | Will Deacon | 2014-10-20 19:49:18 +0200 |
| commit | a8e0aead70b4af957e6b27b82fba849c6179b707 (patch) | |
| tree | 2127e811b50ddf23f21ae678abc129b34e52ded7 /samples/hw_breakpoint | |
| parent | x86: io: implement dummy relaxed accessor macros for writes (diff) | |
| download | kernel-qcow2-linux-a8e0aead70b4af957e6b27b82fba849c6179b707.tar.gz kernel-qcow2-linux-a8e0aead70b4af957e6b27b82fba849c6179b707.tar.xz kernel-qcow2-linux-a8e0aead70b4af957e6b27b82fba849c6179b707.zip | |
documentation: memory-barriers: clarify relaxed io accessor semantics
This patch extends the paragraph describing the relaxed read io accessors
so that the relaxed accessors are defined to be:
- Ordered with respect to each other if accessing the same peripheral
- Unordered with respect to normal memory accesses
- Unordered with respect to LOCK/UNLOCK operations
Whilst many architectures will provide stricter semantics, ARM, Alpha and
PPC can achieve significant performance gains by taking advantage of some
or all of the above relaxations.
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: David Howells <dhowells@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'samples/hw_breakpoint')
0 files changed, 0 insertions, 0 deletions