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| author | Jayachandran C | 2013-12-21 12:22:13 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-24 22:39:46 +0100 |
| commit | c24a8a7a99885d5b986f38f6631f69e7794a3e5e (patch) | |
| tree | a0d6702fc1c45cba157a5734215c509fa4b216c6 /security | |
| parent | MIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resources (diff) | |
| download | kernel-qcow2-linux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.gz kernel-qcow2-linux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.xz kernel-qcow2-linux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.zip | |
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Diffstat (limited to 'security')
0 files changed, 0 insertions, 0 deletions