diff options
| author | Peter Ujfalusi | 2018-11-16 14:41:39 +0100 |
|---|---|---|
| committer | Mark Brown | 2018-11-28 13:40:57 +0100 |
| commit | ca3d9433349ed6a8eadfc9d0ec9e88fff439d0e9 (patch) | |
| tree | 9fadba15dedc67ddbcead14ea7841932d34081a8 /sound/soc/davinci/davinci-mcasp.h | |
| parent | ASoC: davinci-mcasp: Clear TXSTAT register before activating serializers (diff) | |
| download | kernel-qcow2-linux-ca3d9433349ed6a8eadfc9d0ec9e88fff439d0e9.tar.gz kernel-qcow2-linux-ca3d9433349ed6a8eadfc9d0ec9e88fff439d0e9.tar.xz kernel-qcow2-linux-ca3d9433349ed6a8eadfc9d0ec9e88fff439d0e9.zip | |
ASoC: davinci-mcasp: Update PDIR (pin direction) register handling
When McASP is master and the PDIR for the clock pins are configured as
outputs before the clocking is configured it will output whatever clock
is generated at the moment internally.
The clock will switch to the correct rate only when the we start the clock
generators.
To avoid this we must only set the pin as output after the clock is
configured and enabled.
AXR pins configured as outputs behaves somehow interesting as well:
when McASP is not enabled and the pin is selected as output it will not
honor the DISMOD settings for the inactive state, but will pull the pin
down.
Add a new bitfield and mark the pins there which needs to be output and
set the pins only at the time when they will behave correctly.
On stream stop configure the pins back to input which makes them to obey
the global pin configuration regarding to pull up/down.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.h')
| -rw-r--r-- | sound/soc/davinci/davinci-mcasp.h | 29 |
1 files changed, 10 insertions, 19 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h index afddc8010c54..acb024ab6a9d 100644 --- a/sound/soc/davinci/davinci-mcasp.h +++ b/sound/soc/davinci/davinci-mcasp.h @@ -108,27 +108,18 @@ /* * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits - */ -#define AXR(n) (1<<n) -#define PFUNC_AMUTE BIT(25) -#define ACLKX BIT(26) -#define AHCLKX BIT(27) -#define AFSX BIT(28) -#define ACLKR BIT(29) -#define AHCLKR BIT(30) -#define AFSR BIT(31) - -/* * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits + * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode + * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode */ -#define AXR(n) (1<<n) -#define PDIR_AMUTE BIT(25) -#define ACLKX BIT(26) -#define AHCLKX BIT(27) -#define AFSX BIT(28) -#define ACLKR BIT(29) -#define AHCLKR BIT(30) -#define AFSR BIT(31) +#define PIN_BIT_AXR(n) (n) +#define PIN_BIT_AMUTE 25 +#define PIN_BIT_ACLKX 26 +#define PIN_BIT_AHCLKX 27 +#define PIN_BIT_AFSX 28 +#define PIN_BIT_ACLKR 29 +#define PIN_BIT_AHCLKR 30 +#define PIN_BIT_AFSR 31 /* * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits |