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| author | Jie Yang | 2014-10-30 15:57:58 +0100 |
|---|---|---|
| committer | Mark Brown | 2014-10-30 18:06:21 +0100 |
| commit | 0d2135ecadb0b2eec5338a7587ba29724ddf612b (patch) | |
| tree | 27ccb2886e63536fa9852a564d370dbfd8d86eb9 /sound/soc/intel/sst-dsp.h | |
| parent | ASoC: Intel: fix build with runtime PM disabled. (diff) | |
| download | kernel-qcow2-linux-0d2135ecadb0b2eec5338a7587ba29724ddf612b.tar.gz kernel-qcow2-linux-0d2135ecadb0b2eec5338a7587ba29724ddf612b.tar.xz kernel-qcow2-linux-0d2135ecadb0b2eec5338a7587ba29724ddf612b.zip | |
ASoC: Intel: Work around to fix HW D3 potential crash issue
When using clock gatings to save power, there are some known issues:
1. core clock gating (DCLCGE) must be disabled during D0 and D3 entry
and updating SRAM banks (VDRTCTL0).
2. DSP trunk clock gating (DTCGE) can cause FW crashes, disable it in D0.
To align with the new W/A flow from FW team, we must set VDRTCTL0.D3PGD
to 1 (D3 power gating disabled) at first startup and keep it all the time.
ADSP will be in D0 on first boot by BIOS part of WA. Required delays must
be preserved (waiting for HW to stabilize, after enabling CCG, changing
SRAM PG, D3PG).
D3->D0:
1. Disable core clock gating (VDRTCTL2.DCLCGE = 0)
2. Enable other CG apart from DTCG and DCLCG (VDRTCTL2. DCLCGE and DTCGE = 0)
3. Disable D3PG (VDRTCTL0.D3PGD = 1)
4. Power up necessary SRAM and wait at least for 18 clock cycles for every
bank you have powered up
5. Set D0 state(PMCS.PS = 0), wait for HW
6. Restore MCLK (clkctl.smos, disabled in D3 entry point 4)
7. Stall and reset core, set CSR
8. Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us
9. Unreset core
10.Load FW, configure PLL and other necessary things
11.Unstall core
Changing SRAM PG during D0:
1. Disable core clock gating (VDRTCTL2.DCLCGE = 0)
2. Set PG mask
3. Wait at least for 18 clock cycles for every bank you have powered up
4. Enable core clock gating, delay 50 us
D0->D3:
1. Disable core clock gating (DCLCGE = 0)
2. Stall and reset core
3. Power down entire SRAM and wait at least for 18 clock cycles for every bank
(Enable SRAM PG (ISRAMPGE = 0x3FF, DSRAMPGE = 0xFFFFF, D3SRAMPGD = 0), remember
about preserving VDRTCTL0.D3PGD = 1)
4. Shutdown PLL, disable MCLK(clkctl.smos = 0), Enable DTCG to save power
5. Set D3 state(PMCS.PS = 3), delay 50 us
6. Enable core clock gating, delay 50 us
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/sst-dsp.h')
| -rw-r--r-- | sound/soc/intel/sst-dsp.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/sound/soc/intel/sst-dsp.h b/sound/soc/intel/sst-dsp.h index 2753b85ac863..f291e32f0077 100644 --- a/sound/soc/intel/sst-dsp.h +++ b/sound/soc/intel/sst-dsp.h @@ -159,12 +159,18 @@ #define SST_VDRTCTL3 0xaC /* VDRTCTL0 */ -#define SST_VDRTCL0_APLLSE_MASK 1 -#define SST_VDRTCL0_DSRAMPGE_SHIFT 16 -#define SST_VDRTCL0_DSRAMPGE_MASK (0xffff << SST_VDRTCL0_DSRAMPGE_SHIFT) -#define SST_VDRTCL0_ISRAMPGE_SHIFT 6 +#define SST_VDRTCL0_D3PGD (1 << 0) +#define SST_VDRTCL0_D3SRAMPGD (1 << 1) +#define SST_VDRTCL0_DSRAMPGE_SHIFT 12 +#define SST_VDRTCL0_DSRAMPGE_MASK (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT) +#define SST_VDRTCL0_ISRAMPGE_SHIFT 2 #define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT) +/* VDRTCTL2 */ +#define SST_VDRTCL2_DCLCGE (1 << 1) +#define SST_VDRTCL2_DTCGE (1 << 10) +#define SST_VDRTCL2_APLLSE_MASK (1 << 31) + /* PMCS */ #define SST_PMCS 0x84 #define SST_PMCS_PS_MASK 0x3 |