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authorLinus Torvalds2019-08-17 19:36:47 +0200
committerLinus Torvalds2019-08-17 19:36:47 +0200
commit2f478b60118f48bf66eaddcca0d23e80f87a682d (patch)
tree9a4e6341f103e0e758f58b9db3e3d3a325145737 /tools
parentMerge tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa (diff)
parentriscv: Make __fstate_clean() work correctly. (diff)
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Merge tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley: - Two patches to fix significant bugs in floating point register context handling - A minor fix in RISC-V flush_tlb_page(), to supply a valid end address to flush_tlb_range() - Two minor defconfig additions: to build the virtio hwrng driver by default (for QEMU targets), and to partially synchronize the 32-bit defconfig with the 64-bit defconfig * tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Make __fstate_clean() work correctly. riscv: Correct the initialized flow of FP register riscv: defconfig: Update the defconfig riscv: rv32_defconfig: Update the defconfig riscv: fix flush_tlb_range() end address for flush_tlb_page()
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