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-rw-r--r--arch/xtensa/Kconfig17
-rw-r--r--arch/xtensa/configs/nommu_kc705_defconfig1
-rw-r--r--arch/xtensa/include/asm/initialize_mmu.h42
-rw-r--r--arch/xtensa/kernel/head.S2
4 files changed, 41 insertions, 21 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index d575e8701955..524b80722fd0 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -249,6 +249,23 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
If in doubt, say Y.
+config MEMMAP_CACHEATTR
+ hex "Cache attributes for the memory address space"
+ depends on !MMU
+ default 0x22222222
+ help
+ These cache attributes are set up for noMMU systems. Each hex digit
+ specifies cache attributes for the corresponding 512MB memory
+ region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
+ bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
+
+ Cache attribute values are specific for the MMU type, so e.g.
+ for region protection MMUs: 2 is cache bypass, 4 is WB cached,
+ 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,
+ bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,
+ 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is
+ reserved).
+
config KSEG_PADDR
hex "Physical address of the KSEG mapping"
depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
diff --git a/arch/xtensa/configs/nommu_kc705_defconfig b/arch/xtensa/configs/nommu_kc705_defconfig
index 624f9b3a3878..610f622d3c84 100644
--- a/arch/xtensa/configs/nommu_kc705_defconfig
+++ b/arch/xtensa/configs/nommu_kc705_defconfig
@@ -33,6 +33,7 @@ CONFIG_XTENSA_VARIANT_CUSTOM_NAME="de212"
# CONFIG_XTENSA_VARIANT_MMU is not set
CONFIG_XTENSA_UNALIGNED_USER=y
CONFIG_PREEMPT=y
+CONFIG_MEMMAP_CACHEATTR=0xfff2442f
# CONFIG_PCI is not set
CONFIG_XTENSA_PLATFORM_XTFPGA=y
CONFIG_CMDLINE_BOOL=y
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index 42410f253597..10e9852b2fb4 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -177,36 +177,36 @@
#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
XCHAL_HAVE_SPANNING_WAY */
-#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
- (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)
- /* Enable data and instruction cache in the DEFAULT_MEMORY region
- * if the processor has DTLB and ITLB.
- */
+ .endm
+
+ .macro initialize_cacheattr
- movi a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY
+#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
+#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU
+#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.
+#endif
+
+ movi a5, XCHAL_SPANNING_WAY
movi a6, ~_PAGE_ATTRIB_MASK
- movi a7, CA_WRITEBACK
+ movi a4, CONFIG_MEMMAP_CACHEATTR
movi a8, 0x20000000
- movi a9, PLATFORM_DEFAULT_MEM_SIZE
- j 2f
1:
- sub a9, a9, a8
-2:
-#if XCHAL_DCACHE_SIZE
rdtlb1 a3, a5
+ xor a3, a3, a4
and a3, a3, a6
- or a3, a3, a7
+ xor a3, a3, a4
wdtlb a3, a5
-#endif
-#if XCHAL_ICACHE_SIZE
- ritlb1 a4, a5
- and a4, a4, a6
- or a4, a4, a7
- witlb a4, a5
-#endif
+ ritlb1 a3, a5
+ xor a3, a3, a4
+ and a3, a3, a6
+ xor a3, a3, a4
+ witlb a3, a5
+
add a5, a5, a8
- bltu a8, a9, 1b
+ srli a4, a4, 4
+ bgeu a5, a8, 1b
+ isync
#endif
.endm
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 9c4e9433e536..2f76118ecf62 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -181,6 +181,8 @@ ENTRY(_startup)
isync
+ initialize_cacheattr
+
#ifdef CONFIG_HAVE_SMP
movi a2, CCON # MX External Register to Configure Cache
movi a3, 1