diff options
Diffstat (limited to 'arch/blackfin/mach-bf527')
| -rw-r--r-- | arch/blackfin/mach-bf527/Kconfig | 34 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h | 8 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/include/mach/irq.h | 32 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf527/ints-priority.c | 16 |
4 files changed, 45 insertions, 45 deletions
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig index 3cde4beeb214..8438ec6d6679 100644 --- a/arch/blackfin/mach-bf527/Kconfig +++ b/arch/blackfin/mach-bf527/Kconfig @@ -168,29 +168,29 @@ config IRQ_MAC_TX config IRQ_PORTH_INTB int "IRQ_PORTH_INTB" default 11 -config IRQ_TMR0 - int "IRQ_TMR0" - default 12 -config IRQ_TMR1 - int "IRQ_TMR1" +config IRQ_TIMER0 + int "IRQ_TIMER0" + default 8 +config IRQ_TIMER1 + int "IRQ_TIMER1" default 12 -config IRQ_TMR2 - int "IRQ_TMR2" +config IRQ_TIMER2 + int "IRQ_TIMER2" default 12 -config IRQ_TMR3 - int "IRQ_TMR3" +config IRQ_TIMER3 + int "IRQ_TIMER3" default 12 -config IRQ_TMR4 - int "IRQ_TMR4" +config IRQ_TIMER4 + int "IRQ_TIMER4" default 12 -config IRQ_TMR5 - int "IRQ_TMR5" +config IRQ_TIMER5 + int "IRQ_TIMER5" default 12 -config IRQ_TMR6 - int "IRQ_TMR6" +config IRQ_TIMER6 + int "IRQ_TIMER6" default 12 -config IRQ_TMR7 - int "IRQ_TMR7" +config IRQ_TIMER7 + int "IRQ_TIMER7" default 12 config IRQ_PORTG_INTA int "IRQ_PORTG_INTA" diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 8a374c358edf..1fe76d8e0403 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -1163,7 +1163,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) if (val == bfin_read_PLL_CTL()) return; - local_irq_save(flags); + local_irq_save_hw(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SIC_IWR0); iwr1 = bfin_read32(SIC_IWR1); @@ -1177,7 +1177,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); - local_irq_restore(flags); + local_irq_restore_hw(flags); } /* Writing to VR_CTL initiates a PLL relock sequence. */ @@ -1188,7 +1188,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) if (val == bfin_read_VR_CTL()) return; - local_irq_save(flags); + local_irq_save_hw(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr0 = bfin_read32(SIC_IWR0); iwr1 = bfin_read32(SIC_IWR1); @@ -1202,7 +1202,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR0, iwr0); bfin_write32(SIC_IWR1, iwr1); - local_irq_restore(flags); + local_irq_restore_hw(flags); } #endif /* _CDEF_BF52X_H */ diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h index 4e2b3f2020e5..8ea660d8151f 100644 --- a/arch/blackfin/mach-bf527/include/mach/irq.h +++ b/arch/blackfin/mach-bf527/include/mach/irq.h @@ -96,14 +96,14 @@ #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ -#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ -#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ -#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ -#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ -#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ -#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ -#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ -#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ +#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ +#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ +#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ +#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ +#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ +#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ +#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ +#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ @@ -227,14 +227,14 @@ #define IRQ_PORTH_INTB_POS 28 /* IAR4 BIT FIELDS */ -#define IRQ_TMR0_POS 0 -#define IRQ_TMR1_POS 4 -#define IRQ_TMR2_POS 8 -#define IRQ_TMR3_POS 12 -#define IRQ_TMR4_POS 16 -#define IRQ_TMR5_POS 20 -#define IRQ_TMR6_POS 24 -#define IRQ_TMR7_POS 28 +#define IRQ_TIMER0_POS 0 +#define IRQ_TIMER1_POS 4 +#define IRQ_TIMER2_POS 8 +#define IRQ_TIMER3_POS 12 +#define IRQ_TIMER4_POS 16 +#define IRQ_TIMER5_POS 20 +#define IRQ_TIMER6_POS 24 +#define IRQ_TIMER7_POS 28 /* IAR5 BIT FIELDS */ #define IRQ_PORTG_INTA_POS 0 diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c index 8a2367403d2b..f8c8acd73e30 100644 --- a/arch/blackfin/mach-bf527/ints-priority.c +++ b/arch/blackfin/mach-bf527/ints-priority.c @@ -69,14 +69,14 @@ void __init program_IAR(void) ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); - bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | - ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | - ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | - ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | - ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) | - ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | - ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | - ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS)); + bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | + ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | + ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | + ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | + ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | + ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | + ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | |