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Diffstat (limited to 'arch/sh/drivers/pci/pci-sh5.c')
-rw-r--r--arch/sh/drivers/pci/pci-sh5.c55
1 files changed, 25 insertions, 30 deletions
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 7a97438762c8..873ed2b44055 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,8 +89,21 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
return IRQ_NONE;
}
-int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
+static struct resource sh5_io_resource = { /* place holder */ };
+static struct resource sh5_mem_resource = { /* place holder */ };
+
+static struct pci_channel sh5pci_controller = {
+ .pci_ops = &sh5_pci_ops,
+ .mem_resource = &sh5_mem_resource,
+ .mem_offset = 0x00000000,
+ .io_resource = &sh5_io_resource,
+ .io_offset = 0x00000000,
+};
+
+static int __init sh5pci_init(void)
{
+ unsigned long memStart = __pa(memory_start);
+ unsigned long memSize = __pa(memory_end) - memStart;
u32 lsr0;
u32 uval;
@@ -106,12 +119,12 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
return -EINVAL;
}
- pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR");
+ pcicr_virt = (unsigned long)ioremap_nocache(SH5PCI_ICR_BASE, 1024);
if (!pcicr_virt) {
panic("Unable to remap PCICR\n");
}
- PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO");
+ PCI_IO_AREA = (unsigned long)ioremap_nocache(SH5PCI_IO_BASE, 0x10000);
if (!PCI_IO_AREA) {
panic("Unable to remap PCIIO\n");
}
@@ -197,32 +210,14 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
SH5PCI_WRITE(AINTM, ~0);
SH5PCI_WRITE(PINTM, ~0);
- return 0;
-}
+ sh5_io_resource.start = PCI_IO_AREA;
+ sh5_io_resource.end = PCI_IO_AREA + 0x10000;
-void __devinit pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_dev *dev = bus->self;
- int i;
-
- if (dev) {
- for (i= 0; i < 3; i++) {
- bus->resource[i] =
- &dev->resource[PCI_BRIDGE_RESOURCES+i];
- bus->resource[i]->name = bus->name;
- }
- bus->resource[0]->flags |= IORESOURCE_IO;
- bus->resource[1]->flags |= IORESOURCE_MEM;
-
- /* For now, propagate host limits to the bus;
- * we'll adjust them later. */
- bus->resource[0]->end = 64*1024 - 1 ;
- bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
- bus->resource[0]->start = PCIBIOS_MIN_IO;
- bus->resource[1]->start = PCIBIOS_MIN_MEM;
-
- /* Turn off downstream PF memory address range by default */
- bus->resource[2]->start = 1024*1024;
- bus->resource[2]->end = bus->resource[2]->start - 1;
- }
+ sh5_mem_resource.start = memStart;
+ sh5_mem_resource.end = memStart + memSize;
+
+ register_pci_controller(&sh5pci_controller);
+
+ return 0;
}
+arch_initcall(sh5pci_init);