diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display')
3 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index 1e59f4e31a6a..9759d8e790a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -198,7 +198,7 @@ void dce110_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp110->offsets = reg_offsets[params->inst - 1]; + cp110->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -469,6 +469,7 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, struct dc_context *ctx) { + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; /* for dce 11 always use one dram channel for lpt */ @@ -490,7 +491,6 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index 22a5aba073ca..75af2125344b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -404,7 +404,7 @@ void dce112_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp110->offsets = reg_offsets[params->inst - 1]; + cp110->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -797,6 +797,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, struct dc_bios *bp = ctx->dc_bios; struct embedded_panel_info panel_info; + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; compressor->base.options.bits.LPT_SUPPORT = true; /* For DCE 11 always use one DRAM channel for LPT */ @@ -817,7 +818,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index eeedb7c4fe53..77626d7624c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -407,7 +407,7 @@ void dce80_compressor_enable_fbc( /* Keep track of enum controller_id FBC is attached to */ compressor->is_enabled = true; compressor->attached_inst = params->inst; - cp80->offsets = reg_offsets[params->inst - 1]; + cp80->offsets = reg_offsets[params->inst]; /*Toggle it as there is bug in HW */ set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); @@ -777,6 +777,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, struct dc_bios *bp = ctx->dc_bios; struct embedded_panel_info panel_info; + compressor->base.options.raw = 0; compressor->base.options.bits.FBC_SUPPORT = true; compressor->base.options.bits.LPT_SUPPORT = true; /* For DCE 11 always use one DRAM channel for LPT */ @@ -797,7 +798,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, compressor->base.allocated_size = 0; compressor->base.preferred_requested_size = 0; compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; - compressor->base.options.raw = 0; compressor->base.banks_num = 0; compressor->base.raw_size = 0; compressor->base.channel_interleave_size = 0; |